A Multi-Level Ladder Converter Supporting Vertically- Stacked Digital Voltage Domains Kapil Kesarwani, Christopher Schaef, Charles R. Sullivan, and Jason T. Stauth Thayer School of Engineering, Dartmouth College Hanover, NH, USA kapil.kesarwani(at)dartmouth.edu; jason.stauth(at)dartmouth.edu Abstract—Modern digital systems are severely constrained by both battery life and operating temperatures, resulting in strict limits on total power consumption and power density. To continue to scale digital throughput at constant power density, there is a need for increasing parallelism and dynamic voltage/bias scaling. This work presents an architecture and power converter implementation providing efficient power- delivery for microprocessors and other high-performance digital circuits stacked in vertical voltage domains. A multi-level DC- DC converter interfaces between a fixed DC voltage and multiple 0.7 V to 1.4 V voltage domains stacked in series. The converter implements dynamic voltage scaling (DVS) with multi-objective digital control implemented in an on-board (embedded) digital control system. We present measured results demonstrating functional multi-core DVS and performance with moderate load current steps. The converter demonstrates the use of a two-phase interleaved powertrain with coupled inductors to achieve voltage and current ripple reduction for the stacked ladder-converter architecture. I. INTRODUCTION In recent years, semiconductor scaling has driven down system bus voltages of high-performance digital circuits and microprocessors to optimize performance and lifetime of deep-submicron CMOS. In an environment constrained by power-density and operating temperature, this has resulted in significant increases to DC current levels and the need for parallelism to continue to increase performance [1-3]. In a highly parallel architecture, it is becoming increasingly valuable to operate digital sub-systems in different voltage domains to maximize power efficiency for given throughput requirements [2-6]. These trends place significant stress on the power delivery system for high-performance digital architectures. There is a need to improve overall conversion efficiency, support multi-core dynamic voltage scaling (DVS), and at the same time handle increasing conversion ratios relative to system battery and DC bus voltages [5-11]. There have been a range of past efforts on power delivery for high performance microprocessors for servers and portable computing [7-16]. Most efforts have focused on VRM applications which require roughly 12 V to 1 V conversion ratios. Shown in Fig. 1, these efforts have focused on single- core microprocessor load, or multi-core processors with separate converters to implement multi-core DVS [4, 12]. The technology space for the VR application includes complex architectures and control to achieve high efficiency and fast dynamic response. Techniques include load-line regulation [8], current mode and feedforward control [10], and multi- phase coupled magnetics to improve tradeoffs between dynamic response and efficiency [11]. Other efforts have focused on chip-scale power converters that can be feasibly integrated into the high-performance digital system to enable per-core regulation and control. These efforts have included high gain-bandwidth linear regulators [4-6, 12], high-frequency magnetics-based converters [13-14], and high power-density switched-capacitor converters [15- 16]. Such techniques are promising for future power delivery systems but remain elusive due to the need for high power density and efficiency when processing 100% of the power delivered to the digital load. In recent years, alternative architectures have been proposed for digital ICs that help alleviate some of the difficulties in the power delivery system. One such architecture includes stacking digital blocks in vertical voltage domains such that current can be re-used as it flows down the stack. This has been proposed in high-power digital systems [5-6], power delivery sub-systems [12], and even RF power amplifiers [17]. This strategy provides two major benefits for the high-level power delivery system: the total current delivered through the power I/O is reduced, and the conversion ratio of the VR DC- DC converter is moderated. For example, as in [6], by stacking logic domains ‘N’ high, the total current and DC-DC conversion ratio are reduced by approximately ‘N.’ There are several inevitable complexities of this architecture: 1) digital ~3-19 V Core Core Core Core DC DC Sys. Battery or DC Bus Linear Regulators for DVS + - ~1.0 V + - Fig. 1 Traditional VRM application: ~12:1 conversion ratio; separate converters for DVS 978-1-4673-4355-8/13/$31.00 ©2013 IEEE 429