An adaptive digital processor for power efﬁciency enhancement in hybrid supply modulators Atefeh Salimi 1, * ,† , Rasoul Dehghani 1 and Abdolreza Nabavi 2 1 Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran 2 Faculty of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran SUMMARY A novel digital envelope modulator for envelope tracking radio frequency power ampliﬁer is presented in this paper. The proposed modulator consists of a parallel combination of linear class AB and switching class D power ampliﬁers that are controlled digitally. In the previous analog architectures, the requirements needed for the AB operational ampliﬁer such as high-current driving capability, high bandwidth and large output swing is usually obtainable at high overall static power dissipation. The digitally controlled power opamp presented here not only provides the aforementioned requirements but also reduces power dissipation compared with previous work. Furthermore, the digital control of the modulator makes it adaptive to the in- put signal variations in comparison with conventional analog parallel hybrid envelope modulators. The dig- ital processor of the modulator is evaluated with a 45-nm complementary metal oxide semiconductor technology. The overall power consumption of the digital processor is around 142 mW at 1.5-GHz clock fre- quency. As an application, the designed digital class AB is incorporated in a complete envelope modulator architecture. The overall efﬁciency of the modulator, including the digital processor power consumption, is around 82% at an average 32 dBm output power for a 5-MHz input signal. Copyright © 2015 John Wiley & Sons, Ltd. Received 18 October 2014; Revised 23 January 2015; Accepted 26 February 2015 KEY WORDS: digital processor; CMOS; envelope modulators; envelope tracking (ET); power ampliﬁer (PA) 1. INTRODUCTION Modern wireless communication systems tend to use amplitude modulation as well as phase modulation to achieve high data rates. This high data rate results in large Peak to Average Power Ratio (PAPR), which causes the power ampliﬁer (PA) to operate at large power back-off to satisfy the linearity requirements. There are several methods to improve the efﬁciency in the back-off region. Envelope elimination and restoration and envelope tracking (ET) PAs are considerably effective in maintaining the linearity while enhancing the efﬁciency at large power back-offs [1–3]. A simple block diagram of the ET PA is shown in Figure 1. As shown in the ﬁgure, the amplitude and phase of the input signal are separated and ampliﬁed in different paths through the ET PAs. The envelope modulator that is used to amplify the envelope signal affects the overall linearity and efﬁciency of the ET PA systems. Several architectures have been proposed in the literature for envelope modulators, which have different pros and cons. Low-drop-out regulators [4], switch-mode PAs [5–7], series–parallel combined linear and switching PAs [8–11] are the structures that are used in previous work. Low-drop-out regulators have wide bandwidth and low output ripples. However, *Correspondence to: Atefeh Salimi, Department of Electrical and Computer Engineering, Isfahan University of Technol- ogy, Isfahan, Iran. † E-mail: a.salimi@ec.iut.ac.ir Copyright © 2015 John Wiley & Sons, Ltd. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2016; 44:428–443 Published online 2 April 2015 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2085