CTu1A.4.pdf CLEO Technical Digest © OSA 2012 10 Gb/s Error-Free Operation of an All-Silicon C-band Waveguide Photodiode Richard R. Grote, 1,2.* Kishore Padmaraju, 2 Jeffrey B. Driscoll, 1,2 Brian Souhan, 1,2 Keren Bergman, 2 and Richard M. Osgood, Jr. 1,2 1 Microelectronics Sciences Laboratories, Columbia University, New York, NY 10027, USA 2 Department of Electrical Engineering, Columbia University, New York NY 10027, USA * rrg2130@columbia.edu Abstract: We experimentally demonstrate error-free operation of an all Si ion implanted CMOS compatible PIN photodiode at 1.55 μm with 2.5-Gb/s and 10-Gb/s data rates. Detector sensitivity as a function of bias voltage is measured. OCIS codes: (040.6040) Silicon; (040.5160) Photodetectors; (250.3140) Integrated optoelectronic circuits 1. Introduction Silicon photonics, as realized on the silicon-on-insulator (SOI) platform, shows the potential to manifest optical communications within on-chip applications, alleviating the bandwidth bottleneck faced by contemporary microelectronics. Integrated C-band photodetectors (PDs) are of paramount importance in realizing these types of optical links, as they enable the end optical-to-electronic data conversion. These detectors must be high-speed, and CMOS-compatible to support the high data rate conversion of optical signals in highly confined Si “wire” waveguides (SiWG) to the electrical data signals that can be processed by monolithically integrated electronics. However, there exists an inherent difficulty in integrating a material that absorbs in the C-band into a CMOS- compatible SOI based process. Recently, there has been significant progress towards this goal with hybrid integration of III-V materials [1], and also with the integration of Ge [2-4]; albeit, both of these techniques have significant challenges. Hybrid integration is performed as a serial backend process, and does not provide integration into the CMOS line. Similarly, large area growth of crystalline Ge is not possible on a Si substrate due to the intrinsic 4% lattice mismatch between Ge and Si [2]. Various techniques to mitigate this problem have been employed, including small area growth with a SiGe buffer layer and high temperature annealing [2], low temperature growth of a sacrificial high defect Ge layer, followed by a high temperature growth of crystalline Ge [3], and wafer bonding of Ge onto SOI [4]. Although these solutions have produced high performance devices, they require difficult fabrication procedures, and a high thermal budget along with modifications to the standard CMOS process. Alternatively, absorption can be induced in the SiWG itself by creating sub-bandgap defect states via ion implantation. Si + ion implanted SiWG PIN photodiodes have been demonstrated with a bandwidth of > 35GHz and responsivities of 0.8 A/W [5]. These devices are fully CMOS compatible, and do not require any additional high temperature processing. Here we demonstrate error-free data transmission [bit-error-rate (BER) ≤ 10 -12 ] of a 250-μm long Si + ion implanted SiWG PIN PD at 2.5 Gb/s and 10 Gb/s. The sensitivity as a function of bias voltage is also measured. Fig. 1. (a) Cross-Section of a Si + ion implanted Si PIN PD, (b) close up of (a) with WG measurements and doping profiles, (c) top-view optical microscope image, (d) experimental setup. (a)-(c) reprinted from [5]. 2. Experiments and Results The Si + ion implanted SiWG PIN PDs were fabricated on the CMOS line at MIT Lincoln Laboratory, as described in [5-7], with dimensions given in Fig. 1(a) and Fig. 1(b). Figure 1(c) shows a top view of the tested photodiode