An Algorithm for Checking Slicing Floorplan Based on HPG and Its Application zy Changwen Zhuang, Xiaoke Zhu Research zyxwvutsrqp & Development Division JEDAT Innovation Inc. zyxwvutsr 2-5, Hibikino, Wakamatsu, Kitakyushu Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani Information and Media Sciences, University of Kitakyushu 1 zyxwvut -1, Hibikino, Wakarnatsu, Kitakyushu {changwen, xiaoke}@jedat.co.jp { zyxwv takasima,nakatake,kajitani}@env.kitakyu-u.ac.jp zyx Abstract- Slicing floorplan has been intensively re- searched all the time for its naive property to the cnt- based placement, soft-module packing, designers' inten- sion even after packing and general floorplan represen- tations were proposed. HPG, one easy-to-understand general floorplan representation, were proved to get the optimal solution in shorter time than other representa- tions. In this paper, we present an algorithm to show another outstanding feature of HPG. By using this algo- rithm, we can search and find optimal slicing floorplan easily, which can provide more flexibility for placement and routing tools. Experiments show the effectiveness and promising perspective of our algorithm. Keywords: floorplan, placement, HPG, slicing I. INTRODUCTION With increasing design complexity, the need for an effi- cient and flexible placement tool becomes more crucial. Since Nakatake et al. proposed the first BSG packing representation[3], Sequence Pair[4], 0-tree[S], B*-tree[6] and TCG[7], etc. were presented one after another. Almost at the same, two floorlan representation, Q-sequence[S][ IO] and CBL[9] were innovated to make placement algorithms run faster. Zhuang et al. introduced a Hamilton Path-based Graph, named HPG to represent a general floorplan, and could get optimal solution in shorter time, while making the feature of the floorplan explicit. More recently, Zhang et al, presented new representation named zyxwvutsr SS which can unify many existing representations. However, before the emerging of packing and general floorplan representations, much efforts have been put on slicing representation. In 1982, Otten [I] proposed an auto- mated floorplanning using the slicing structure, which was later represented by a polish expression by D. F, Wong and Liu [Z]. Afler getting either a slicing floorplan or a general floor- plan, we will put at most one circuit module (one module may has several realizations) into a room in the floorplan and optimize the size of the floorplan, which zyxwvut is called siz- ing problem. Shi [ 1 I] settled the sizing problem in worst case zyxwvutsrqpon O(NlogN), where N is the total number realizations and showed this is a lower bound. Considering the sim- temperature Fig. 1 search solution in two spaces ulated annealing method exploited in today's packing and general flooplan algorithms, sizing problem of slicing floor- plan is more predictive. In fact, for general floorplans, Stockemyer)[l2] et al. proved that the sizing problem is strong NP-complete. Slicing floorplan has smaller space complexity hut may deviate from optimal area solution, while general flooplan suffers from large solution space. Our contributions of this paper are: (I) we first time present an fast algorithm to check a floorplan is slicing or not based on the&?neral floorplan representation, HPG. So designers can get optimal general floorplan and slicing floorplan by using tbe same floorplan representation, which implys more flexibility in the design. (2) With the slicing checking algorithm based on HPG, we make fully use of advantages of slicing floorplan and general floorplan. As shown in Fig. I, the simulated annealing program can ex- ploit slicing floorplans and explore solution in a small space at first, and finally adopt both kinds of floorplans after tem- perature come to a specified value T, which is near final temperature. With smaller solution space, we can find the good result in shorter runtime. The paper is organized as follows. Section 2 formulates the problem. Section 3 introduces HPG. Section 4 discusses the slicing checking algorithm. Section 5 shows the exper- imental results. Finally, section 6 concludes the paper. 11. PROBLEM F O R M U L A T I O N Given n modules with widths and heights (U,, hi), 15 i S 71, the placementproblemis to arrange these modules on a chip without overlap while optimizing a variety of objec- tives, such as chip area, total wire length, timing, crosstalk, etc. Both floorplan and packing representations can be used 0-7803-8647-7/04/$20.00 0 2004 IEEE. 1223