IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 _______________________________________________________________________________________ Volume: 04 Issue: 01 | Jan-2015, Available @ http://www.ijret.org 410 A 2-STAGE DATA WORD PACKET COMMUNICATION DECODER USING RATE 1-BY-3 VITERBI DECODER AND PARITY GENERATOR Doli Vyas 1 , Shraddha Shrivastav 2 , Rita Jain 3 1 Department of Electronics and Communication, Laxmi Narain College of Technology, Madhya Pradesh, India 2 Department of Electronics and Communication, Laxmi Narain College of Technology, Madhya Pradesh, India 3 Department of Electronics and Communication, Laxmi Narain College of Technology, Madhya Pradesh, India Abstract In the field of consumer electronics the high speed communication technology applications based on hardware and software control are playing a vital role in establishing the benchmarks for catering the operational requirements of the electronic hardware to fulfil the consumer requirements in wired and wireless communication. In the modern era of communication electronics decoding and encoding of any data(s) using high speed and low power features of FPGA devices [1] based on VLSI technology offers less area, hardware portability, data security, high speed network connectivity [2], data error removal capability, complex algorithm realization, etc. Viterbi decoder is a high rate decoder that is very commonly and effectively used method in modern communication hardware. It involves Trellis coded modulation (TCM) scheme for decoding the data. The viterbi decoder is an attempt to reduce the power, speed [1], and cost as compared to normal decoders for wired and wireless communication. The work in this paper proposes a improved data error identification probability design of Viterbi decoders for communication systems with a low power operational performance. The proposed design combines the error identification capability of the viterbi decoder with parity decoder to improve the probability of the overall system in identifying the error during the communication process. Among various functional blocks in the Viterbi decoder, both hardware complexity and decoding speed highly depends on the architecture of the Decoder. The operational blocks of viterbi decoder are combined with parity testing block to identify the error in the viterbi decoded data using parity bit. The present design proposes a multi-stage pipelined architecture of decoder. The former stage is the viterbi decoding stage and the later stage is the parity decoding stage for the identification of error in the communicated data. Any Odd number of errors occuring in the recovered data from the former decoding stage can be identified using the later decoding stage. A general solution to derive the communication using conventional viterbi decoder is also given in this paper. Implementation result of proposed design for a rate 1/3 convolutional code is compared with the conventional design. The design of proposed algorithm is simulated and synthesized successfully Xilinx ISE Tool [3] on Xilinx Spartan 3E FPGA. Keywords: ACS (Add-Compare-Select), Convolutional Code Rate, Error probability, FPGA, Low Power, Parity Encoder, Pipelining, Trace Back, Viterbi Decoder, Xilinx ISE. --------------------------------------------------------------------***---------------------------------------------------------------------- 1. INTRODUCTION Typically, a TCM system employs a high-rate convolutional code that leads to a high complexity of the Viterbi decoder even for moderate constraint length of the convolutional code. A lot of work has already been proposed on Viterbi decoder. Use of rate-3/4 convolutional code is proposed for 4-D TCM system for deep space communications in [4]. Reduced-state sequence decoding (RSSD) method [5], M- algorithm [6] and T-algorithm [7, 8], Viterbi decoder based on over-scaling supply voltage [9], power efficiency in T- algorithm [10, 11] has been already proposed for speed and power based optimization of Viterbi decoder. General solutions for low-power VD design have already been well studied by existing work. T-algorithm is more commonly used than M-algorithm in practical applications. In the M- algorithm a sorting process is used in a feedback loop while in T-algorithm the optimal path matric search is performed. Searching for the optimal PM in the feedback loop still reduces the decoding speed. A Gate Diffusion Input circuits for asynchronous design is proposed in [12], Viterbi decoder based on modified register-exchange method [13], a scheme based on Verilog language for the implementation of high- speed and low power consumption bi-directional Viterbi decoder [14], various logic styles (CMOS, Pseudo NMOS and Dynamic logic) based design of circuits at ACS level [15], Gate Diffusion Input Logic (GDIL) based implementation [16], etc. are also proposed designs to improve speed of Viterbi decoder. A high-rate convolutional code suffers from a severe degradation of bit-error-rate (BER) performance due to inherent drifting error between the estimated the accurate path matric and the optimal path matric. The computational overhead and decoding latency of the data decoding system are to be taken into consideration along with the other performance criteria to meet the required performance of the decoding system. In this work, we analyzed the conventional Viterbi decoder algorithm and the proposed Viterbi decoder design algorithm for a rate 1/3 code. The proposed method is based on the performance of Viterbi Decoder in line with Parity Decoder to improve the data error identification probability. The block diagram of proposed encoder and decoder are shown in Fig-1 and Fig-2