IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 9, SEPTEMBER 2005 607 Characteristics of Transistors Fabricated on Silicon-on-Quartz Prepared Using a Mechanically Initiated Exfoliation Technique Xuejie Shi, K. Henttinen, T. Suni, I. Suni, and Man Wong Abstract—Single-crystalline silicon thin film on fused quartz (SOQ) was prepared using a technique based on wafer bonding and mechanically initiated exfoliation. MOSFETs fabricated on the resulting SOQ were characterized. The measured low-field electron effective mobility was cm V s, which is 35% higher than that extracted from reported “universal curve” for electron effective mobility. Consistent with the mobility enhance- ment, a tensile strain of 0.25% in the SOQ was deduced from Raman spectroscopy. At cm V s, no enhancement in hole effective mobility was observed. Index Terms—Ion-cutting, mobility enhancement, MOSFETs, silicon-on-quartz (SOQ), strained-silicon. I. INTRODUCTION T HE technique of wafer bonding has been used to realize single-crystalline silicon (Si) thin film on a quartz sub- strate (SOQ). Though etch-back has been employed to obtain SOQ after bonding [1], layer transfer by hydrogen-induced ex- foliation [2], [3] is preferred because of reduced material waste and improved thickness control. Applications that potentially could exploit the high transparency and the high resistivity of a quartz substrate were display [1] and radio frequency [2] systems, respectively. It is expected that devices built on SOQ have similar advantages of small junction capacitance and good short-channel behavior as those built on silicon-on-insulator substrates [4]. Though glass is similar to quartz in these two attributes, the ability of the latter to withstand high-temperature processing is expected to lead to devices superior to those built on glass [5]. Because of the significant difference between the thermal expansion coefficients (CTE) of Si and quartz, debonding or cracking typically occurs before reaching the temperature of 400 C–600 C [3] required for thermally initiated exfoliation. Reported here are a technique of “cold ion-cutting” based on room temperature, mechanically initiated exfoliation [2], [6], and the characteristics of the resulting FETs. A low-field electron effective mobility of cm V s was Manuscript received March 29, 2005; revised June 7, 2005. This work was supported under a Grant from the Research Grants Council of the Hong Kong Special Administrative Region. The review of this letter was arranged by Editor M. Ostling. X. Shi and M. Wong are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail: eemwong@ee.ust.hk). K. Henttinen, T. Suni, and I. Suni are with VTT Center for Microelectronics, Espoo Finland. Digital Object Identifier 10.1109/LED.2005.853649 measured, which is 35% higher than that extracted from reported “universal” curve [7]. Such enhancement is consistent with the presence of lattice tensile strain, which was indeed revealed using Raman spectroscopy. Similar increase in has been reported for transistors built on resolidified polycrystalline Si [8] on quartz, with the tensile strain formed during cooling attributed to the larger CTE of Si. II. MECHANICAL EXFOLIATION AND FET FABRICATION (100)-oriented p-type Si wafers with a resistivity of 1–2 cm were implanted with 50 keV hydrogen ions H at a dose of cm through a 100-nm thermally grown screen oxide. The oxide was removed before pairs of Si and fused quartz wafers were conditioned by immersing in an RCA-1 solution for 10 min and activated in an argon plasma for 30 s [9]. Bonding was done in a vacuum at room temperature using an Electrovision EV801 wafer bonder. The interfacial bonding strength was enhanced by annealing for 6–8 h at 250 C, reached after a slow temperature ramp of . Cooled to room temperature, the bonded pair was held on the quartz side on a vacuum chuck before mechanical exfoli- ation was done using a 0.1-mm-thick metal blade. After the exfoliation, 70–100 nm of the transferred Si was removed by chemical–mechanical polishing and 168 nm with an average surface roughness of 0.7 nm was retained. The SOQ was subsequently annealed at 600 C for 60 min and 1000 C for 60 min in nitrogen, to recover the original p-type conductivity [10] and to enhance the bonding strength. Device fabrication started with the growth of 153-nm thermal oxide, 50 nm of which was removed before 90 keV phosphorus ions at a dose of cm were implanted through selected regions of the remaining oxide layer to form the n-type regions in which the p-type FETs would be built. The active islands, then 100 nm thick, were defined after removing the remaining oxide layer. A 28-nm-thick gate oxide was grown using dry oxidation at 950 C. This was followed by low-pressure chemical vapor deposition (LPCVD) at 620 C and patterning of 300-nm polycrystalline Si as the gate electrode. 60-keV phosphorous and 25-keV boron ions, at the same dose of cm , were implanted to form the self-aligned gate/source/drain regions of the n- and p-type FETs, respectively. The dopants were subsequently activated at 900 C in nitrogen for 90 min. Contact holes were opened through a 500-nm LPCVD low temperature oxide insulating layer. This was followed by the deposition and definition of 0741-3106/$20.00 © 2005 IEEE