Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Speciﬁcations Prabhat Mishra Nikil Dutt Hiroyuki Tomiyama pmishra@cecs.uci.edu dutt@cecs.uci.edu tomiyama@is.nagoya-u.ac.jp Center for Embedded Computer Systems Dept. of Information Engineering University of California, Irvine, CA 92697, USA Nagoya University, Nagoya 464-8603, Japan CECS Technical Report #03-25 Center for Embedded Computer Systems University of California, Irvine, CA 92697, USA July 28, 2003 Abstract As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. A signiﬁcant bottleneck in the validation of such systems is the lack of a golden reference model. Thus, many existing techniques employ a bottom-up approach to architecture validation, where the functionality of an existing pipelined architecture is, in essence, reverse-engineered from its implementation. Our validation techniqueis com- plementary to these bottom-up approaches. Our approach leverages the system architect’s knowledge about the behavior of the pipelined architecture, through Architecture Description Language (ADL) con- structs, and thus allows a powerful top-down approach to architecture validation. The most important requirement in top-down validation process is to ensure that the speciﬁcation (reference model) is golden. Earlier, we have developed validation techniques to ensure that the static behavior of the pipeline is well-formed by analyzing the structural aspects of the speciﬁcation using a graph based model. In this paper, we verify the dynamic behavior by analyzing the instruction ﬂow in the pipeline using a Finite State Machine (FSM) based model to validate several important architectural properties such as determinism, ﬁniteness, and execution style (e.g., in-order execution) in the presence of hazards and multiple exceptions. We applied this methodology to the speciﬁcation of a representative pipelined processor to demonstrate the usefulness of our approach.