IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006 289 New Low-Voltage Class AB/AB CMOS Opamp With Rail-to-Rail Input/Output Swing Jaime Ramírez-Angulo, Fellow, IEEE, Milind-Subhash Sawant, Shanta Thoutam, Student Member, IEEE, Antonio J. López-Martín, Member, IEEE, and Ramon G. Carvajal, Senior Member, IEEE Abstract—A new low-voltage CMOS Class AB/AB fully differen- tial opamp with rail-to-rail input/output swing and supply voltage lower than two drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The opamp is characterized by low static power consump- tion and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5- m CMOS technology verify the scheme operating with 0.9-V supplies and close to rail-to-rail input and output swing. Index Terms—Amplifiers, analog circuits, CMOS integrated cir- cuits, low power design, low-voltage circuits. I. INTRODUCTION T HE NATURAL choice for operational amplifiers in low-supply applications is the two stage fully differential Class AB topology [1]. A power efficient Class AB/AB opamp based on the use of a Class AB “Pseudodifferential” input stage with a Class AB output stage was recently reported in [2]. The opamp has high slew rate obtained with low static power dissipation under low supply-voltage restrictions. The main drawbacks are: 1) the opamp has very limited input signal swing and 2) both the pseudo-differential input stage and the CMFN require sensing of the common input and output voltages. This is done in [2] using large valued silicon area intensive resistors that degrade input impedance and gain, or in [3], [4] through relatively complex circuits that require additional silicon area and power dissipation and that also limit severely input and output swings. In this paper, we Manuscript received July 20, 2004; revised February 20, 2005 and June 29, 2005. This work was supported in part by the Spanish Ministry of Science and Technology under Project TIC2003-07307-C02. This paper was recommended by Associate Editor A. Korotkov. J. Ramírez-Angulo is with the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003-8001 USA (e-mail: jramirez@nmsu.edu). M.-S. Sawant was with the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003-8001 USA. He is now with Qualcomm Incorporated, San Diego, CA USA (e-mail: milind@nmsu.edu). S. Thoutam is with the Klipsch School of Electrical and Computer Engi- neering, New Mexico State University, Las Cruces, NM 88003-8001 USA, and also with Freescale Semiconductors Inc. (Motorola) Austin, TX USA (e-mail: Shanta.Thoutam@freescale.com). A. J. López-Martín is with the Department of Electrical and Electronic Engi- neering, Public University of Navarra, Campus Arrosadia, E-31006 Pamplona, Spain (e-mail: antonio.lopez@unavarra.es). R. G. Carvajal is with the Department of Electronic Engineering, University of Seville, E- 41092 Sevilla, Spain (e-mail: carvajal@gtex10.us.es). Digital Object Identifier 10.1109/TCSII.2005.862027 present a simplified version of this circuit that overcomes the above mentioned drawbacks and features almost rail-to-rail input/output swings. It is not based on the traditional rail-to-rail architecture that uses complementary differential input stages [5] and requires a minimum supply voltage of two gate–source voltage drops plus two drain–source saturation voltages, i.e., . These traditional schemes also require additional circuitry (and power) in order to achieve a constant input stage transconductance gain for optimum compensation. In our case, the multiple-input-floating-gate (MIFG) transistors are used instead. MIFG transistor circuits have been reported that achieve low-voltage operation [6] with . Other low-voltage approaches using MIFG transistor are based on injecting (or removing) charge from the floating gate. This requires circuits with tunneling injectors and large programming voltages. The approach used in this paper is based instead on shifting the quiescent voltage of the floating gate in direction of one of the supply rails by connecting an input terminal of an MIFG transistor to the corresponding supply rail [9]. This minimizes the supply requirements and provides rail-to-rail input signal swing with constant . Until recently, floating-gate circuits suffered from reliability problems since charge trapped in the floating gates during the fabrication process could lead to very large dc offset voltages. Recently, a simple solution was reported [7] that removes the charge generated during fabrication without additional post-pro- cessing steps like UV shining or complex circuitry. This solu- tion consists in including contacts between the poly I gate layer and all metal layers. These contacts lead to a short circuit be- tween the poly I and poly II layer at some point during fabri- cation before metal is patterned. The short circuit is removed once the metal layer is patterned. It prevents storage of charge in the poly I floating gate. The effectiveness of this technique has been verified by the authors in several circuits besides the ones reported here. The circuit proposed here employs MIFG transis- tors and this technique: 1) To attain rail-to-rail input and output swings with constant ; 2) to implement very compact contin- uous-time rail-to-rail common-mode input and output sensing circuits, and 3) to achieve low-voltage operation. II. FLOATING-GATE TRANSISTORS Fig. 1 shows a differential pair with floating-gate transistors with two inputs each. As described in [6], for low-voltage appli- cations a relatively large valued capacitor connected to a dc voltage can be used in order to bring the quiescent floating-gate voltages close to one of the supply rails ( for nMOS transistors, for pMOS transistors). This 1057-7130/$20.00 © 2006 IEEE