1 Using Transmission Lines for Global On-Chip Communication Aaron Carpenter, Jianyun Hu, Jie Xu, Michael Huang, Hui Wu, and Peng Liu Abstract—The growing number of cores in chip multi- processors increases the importance of interconnection for overall system performance and energy efficiency. Compared to traditional distributed shared-memory architectures, chip- multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. Worsening wire delays, energy-inefficient routers, and the decreased importance of in-field scalability, make the conventional packet-switched network-on-chip a less attractive option. An alternative solution uses well-engineered transmission lines as communication links. These transmission lines, along with simple, practical circuits using modern CMOS technol- ogy, can provide low latency, low energy, high throughput channels which can be used as a shared-medium point- to-point link. The design of the transmission lines and transceiver circuits has important architectural impact. This paper includes a first-step design effort for these compo- nents, particularly when used for a globally shared-medium bus. For medium-scale CMPs, this interconnect backbone can eliminate the need for packet switching and provide energy, as well as performance benefits when compared to a conventional mesh interconnect. We will provide a design of such a system from the ground up, including design of the transmission lines, transceiver circuits, and a simple, yet effective, architectural design for a shared- medium interconnect, and show that such a design can be a compelling alternative to packet-switched networks for CMPs. I. I NTRODUCTION As the number of cores integrated into a single chip steadily increases, an important component in chip multiprocessors (CMPs) is the on-chip interconnect. For a number of reasons, packet-switched interconnect is often accepted as the de facto solution [26], [42]. A packet switched network offers numer- ous advantages such as throughput scalability and modularity. However, it is not without drawbacks. Routers are complex structures that occupy significant chip real-estate and consume This work is supported in part by NSF under the grants 0901701, 0829915, and 0747324, and by the NSFC under grant 61028004. Copyright (c) 2012 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs- permissions@ieee.org. A. Carpenter is with the Electrical & Computer Engineering Dept. at Binghamton University, carpente@binghamton.edu J. Hu, J. Xu, M. Huang, and H. Wu are with the Electrical & Computer Engineering Dept. at the University of Rochester, {jianyun.hu, jie.xu, michael.huang, hui.wu}@rochester.edu P. Liu is with the Information Science & Electronics Engineering Dept. at Zhejiang University, liupeng@zju.edu.cn significant power [45]. Repeated packet relaying adds latency to communication and can be an important performance issue, especially for simpler topologies with large network diameters such as ring or mesh. These disadvantages are upfront costs paid even when the applications do no need scalable throughput. As such, alternative architectures should be explored. Transmission line based interconnects are a promising candidate. A transmission line (TL) allows high signaling rate, speed-of- light propagation velocity, and can potentially provide sufficient throughput for a range of CMPs, such that packet relaying can be avoided altogether. TL-based designs have been used in the context of microprocessors, but the specific design used is often studied and described in an ad-hoc fashion. A TL link has a large degree of freedom in designing the channel medium, the coding scheme, and the circuitry in the signaling chain and offers a vast range of trade-offs between costs and benefits. There is a lack of comprehensive design space studies to help architects navigate the design space and make optimal system-wide trade- offs. However, the design choices made at the circuit level have a significant impact on the characteristics of the architectural implementation, and vice versa. Figure 1 qualitatively illustrates a TL and circuit design spaces. This paper presents an exploration of the design space of TL circuitry, and provides a simple, yet effective architectural design, using the TL links as a shared interconnect backbone. The rest of the paper is organized follows: Section II gives some background and related work. Section III discusses the transmission line and transceiver circuit design spaces. Sec- tion IV describes the architectural design in depth, and Section V evaluates the design. Section VI concludes. Bit-Rate (per line) Energy Digital Analog OOK Complex Encoding Mixed- Signal Increasing Complexity Fig. 1: Illustration of transmission line link system design space. II. BACKGROUND &RELATED WORK Transmission lines are common components in RF and mi- crowave circuits. The characteristics of the transmission lines, such as impedance, loss, propagation delay, dispersion and