© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 6029 wileyonlinelibrary.com COMMUNICATION Ultra-Low Voltage and Ultra-Low Power Consumption Nonvolatile Operation of a Three-Terminal Atomic Switch Qi Wang,* Yaomi Itoh, Tohru Tsuruoka, Masakazu Aono, and Tsuyoshi Hasegawa* Dr. Q. Wang, Y. Itoh, Dr. T. Tsuruoka, Prof. M. Aono, Prof. T. Hasegawa World Premier International (WPI) Center for Materials Nanoarchitectonics (MANA) National Institute for Materials Science (NIMS) Namiki 1-1, Tsukuba, Ibaraki 305-0044, Japan E-mail: wangqi77@lzu.edu.cn; thasega@waseda.jp Dr. Q. Wang, Y. Itoh, Dr. T. Tsuruoka, Prof. T. Hasegawa Japan Science and Technology Agency CREST Chiyoda, Tokyo 102-0075, Japan Dr. Q. Wang School of Physical Science and Technology Lanzhou University Lanzhou 730000, China Prof. T. Hasegawa Faculty of Science and Engineering Waseda University 3-4-1 Ookubo, Shinjuku-ku, Tokyo 169-8555, Japan DOI: 10.1002/adma.201502678 This structure shows volatile (<2 V) and nonvolatile switching (>2 V), depending on the gate bias range used. Here, it should be noted that nucleation of a metal cluster should occur at the cathodes, i.e., a source and a drain, in the three-terminal operation. In two-terminal operations, filament growth is observed both from a cathode side [18] and from an anode side, [7,19–23] depending on an ionic transfer material used. It is understood that nucleation of a metal cluster followed by a filament growth is determined by the competition between migration and reduction of metal cations in an ionic transfer material. [7] Therefore, choice of an ionic transfer material is important for achieving the three-terminal operation. Although we demonstrated the three-terminal operation, fur- ther significant reduction in the operating bias, so as to lower the operating power, continues to be a difficult challenge that must be overcome in order to compete with semiconductor transistors and other new conceptual logic devices. Cyclic endur- ance, especially in nonvolatile operation, and switching speed are additional issues that remain for the device. Reduction of the size of the gap between the source and the drain (10 nm in the previous study) seemed to be the most effective solution to the issues because such reduction should enable switching with the formation/annihilation of a smaller metal nucleus, which is easily formed and dissolved with a smaller gate bias. In order to achieve the necessary size reduction, we intro- duced an inductive coupled plasma reactive ion etching (ICP- RIE) process when fabricating the sidewall of a multilayer of Pt/Ti (source), SiO 2 , Pt/Ti (drain), to which Ta 2 O 5 , then Ag (or Cu) was deposited. Focused ion beam (FIB) etching, used in the previous study, makes the edges of the Pt/Ti layers dull because of the large difference in etching rates between Pt/Ti and SiO 2 , as shown in Figure 1b. As a result, the effective gap between the source and the drain becomes larger than the thickness of an inserted SiO 2 layer. Although there is usually a much larger difference in etching rates for metals and oxides in ICP-RIE than there is in FIB, we succeeded in optimizing the condi- tions by using SF 6 as a reactive gas. We created a sharp edge of Pt/Ti layers, as shown in Figure 1c, where the gap between the source and the drain is determined by the thickness of an inserted SiO 2 layer. Ta 2 O 5 layer porosity is thought to be another key character- istic for smaller gate bias operation, because larger spaces make ion drift much easier. To confirm this, we employed an elec- tron-beam (EB) deposition technique for a Ta 2 O 5 layer, which was formed by radio frequency (RF) sputtering in the previous studies. This technique was chosen because EB-deposited Ta 2 O 5 layers show less density (6.8 g cm -3 ) than Ta 2 O 5 layers depos- ited by RF sputtering (7.6 g cm -3 ), thereby increasing the dif- fusion constant of metal cations in the Ta 2 O 5 layer. In fact, the forming voltage of a two-terminal Ag/Ta 2 O 5 (EB deposited)/Pt A large variety of nanometer-scale ionic devices have been studied in recent years in an attempt to overcome the phys- ical and economic limitations of the semiconductor devices currently in use. [1–7] For memory applications, two-terminal structures have demonstrated excellent operation, such as superior switching speeds (sub-nanosecond) and switching endurance (up to 10 12 ). [8–10] The novel characteristics of these devices, such as their small size, low power consumption, and nonvolatility, [11,12] are expected to overcome present limitations. Two-terminal structures have also been used for logic applica- tions. For instance, ionic cell arrays have demonstrated basic logic operations. [13,14] The three-terminal structure has an advantage over two- terminal structures in logic applications, in that it can be con- trolled by a gate that is electrically separated by a signal line, i.e., a source and a drain. This separation also enables switching with very small power consumption, in contrast to two-terminal structures that usually require large currents, especially in their turning off process. [15] We previously demonstrated three-terminal operation using atomic-switch technology [16,17] in which metal cations (e.g., Ag + and Cu Z+ ) are supplied into an ionic transfer layer (e.g., Ta 2 O 5 ) from a gate, and are brought to a channel region (i.e., a source and a drain), resulting in the nucleation of a metal cluster bridging the source and the drain. Application of an opposite polarity bias dissolves the metal cluster, resulting in switching the device off, as shown in Figure 1a. High on/ off ratios, of up to eight orders of magnitude, and very low gate leakage currents (3 × 10 -5 pA nm -2 ) were demonstrated using an Ag(Cu)/Ta 2 O 5 /Pt, Pt structure, where a source Pt layer and a drain Pt layer were separated by a 10 nm thick SiO 2 layer. Adv. Mater. 2015, 27, 6029–6033 www.advmat.de www.MaterialsViews.com