An Approach to the Design of Multistandard ΣΔ Modulators A. MORGADO, J.M. DE LA ROSA, R. DEL RÍO, F. MEDEIRO, B. PÉREZ-VERDÚ, F.V. FERNÁNDEZ, AND A. RODRÍGUEZ-VÁZQUEZ Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC) Ed. CNM-CICA, Av. Reina Mercedes s/n, 41012 Sevilla SPAIN Abstract: - This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach. Key-Words: - Data converters, Sigma-Delta, Wireless, Multistandard 1 Introduction The growth of wireless communication technologies has prompted the emergence of multitude of new applications and standards. These new standards —like IEEE 802.11 WLAN and UMTS— are com- plementing rather than replacing the existing ones —such as GSM— giving rise to the so-called univer- sal or multistandard transceivers. These systems are able to operate over a variety of specifications, thus benefiting of the different services and functions offered by co-existing wireless standards [1]. Multistandard transceivers need to be implemented by reconfigurable building blocks that can be adapted to each specification by adjusting their circuit parame- ters with adaptive power consumption. One of the most challenging building blocks is the A na- log-to-D igital C onverter (ADC), because of the wide range of sampling rates and dynamic ranges required to digitize the signals of each individual standard [2]. S igma-D elta M odulators (ΣΔMs) are good candi- dates for implementing the ADC in multistandard, multimode communication systems [3][4]. They com- bine redundant temporal data (oversampling) to reduce quantization noise and filtering (noise shaping) to push this noise out of the signal band. On the one hand, these characteristics result in high-performance, robust ADCs with lower sensitivity to circuitry imperfections than Nyquist-rate ADCs, thus making easier to include reconfigurability and programmability functions with- out significant performance degradation. On the other, ΣΔMs trade analog accuracy by signal processing, thus facilitating their integration in modern deep-submicron VLSI technologies, more suited to implement fast digi- tal circuits than precise analog functions. Several multistandard ΣΔM ICs have been reported up to now [5]-[9]. Most of them are based on reconfiguring architecture-level parameters (modula- tor order, oversampling ratio and/or number of bits of the internal quantizers), whereas less emphasis is nor- mally put at circuit-level parameters. This paper presents design considerations applica- ble to expandible cascade ΣΔMs intended for multi- standard receivers —covering GSM, Bluetooth, UMTS, and WLAN. A top-down design procedure is described from system-level to building-block level, putting special emphasis on optimizing the circuit design for different operation modes. To this purpose, different strategies are adopted at both architecture- and circuit-level in order to fulfill specifications with minimum power consumption. 2 Modulator Specifications The ΣΔM in this paper has been designed to meet the requirements of D irect-C onversion R eceivers (DCRs) like that shown in Fig.1. This receiver architecture is commonly used in multistandard applications because it eliminates the need for both IF and image reject fil- tering and requires only a single oscillator and mixer [10]. In order to cope with the requirements of the dif- ferent standards, separate (switchable) RF hardware paths (normally one per standard) are used whereas a single, digitally-programmed baseband section (from the mixer to the ADC) is implemented [11]. The receiver must detect a wanted signal at the antenna in presence of strong unwanted signals (inter- feres) without causing a degradation of the receiver performance. In multistandard implementations, the 4th WSEAS International Conference on ELECTRONICS, CONTROL and SIGNAL PROCESSING, Miami, Florida, USA, 17-19 November, 2005 (pp.229-234)