Parallel Algorithms for Logic Synthesis using the MIS Approach Kaushik De John A. Chandy Sumit Roy Steven Parkes Prithviraj Banerjee LSI Logic Corporation University of Illinois Sierra Vista Research Milpitas, CA 95035 Urbana, IL 61801 Santa Clara, CA 95055-3758 kaushik@lsil.com jchandy,sroy,banerjee @crhc.uiuc.edu parkes@sierravista.com Abstract Combinational logic synthesis is a very important but compu- tationally expensive phase of VLSI system design. Parallel pro- cessing offers an attractive solution to reduce this design cycle time. In this paper, we describe ProperMIS, a portable par- allel algorithm for logic synthesis based on the MIS multi-level logic synthesis system. As part of this work, we have developed novel parallel algorithms for the different logic transformations of the MIS system. Our algorithm uses an asynchronous message- driven computing model with no synchronizing barriers separat- ing phases of parallel computation. The algorithm is portable across a wide variety of parallel architectures, and is built around a well-defined sequential algorithm interface, so that we can ben- efit from future expansion of the sequential algorithm. We present results on several MCNC and ISCAS benchmark circuits for a va- riety of shared memory and distributed processing architectures. Our implementation produces speedups of an average of 4 on 8 processors. 1 Introduction Combinational logic synthesis is the optimization of a logic design to realize a specific combinational function in either two level or multilevel form, and typically optimizes the area or delay of the re- sultant circuit. Efficient algorithms for two-level logic minimiza- tion include ESPRESSO [1] and for multilevel logic optimization, SOCRATES [2], MIS [3], SYLON-XTRANS [4], and BOLD [5]. Since logic synthesis is very compute intensive, parallel pro- cessing is fast becoming a desirable solution to reduce the large amounts of time spent in VLSI circuit design. This has been recognized by several researchers in VLSI CAD, as many have started to investigate parallel algorithms for problems in logic syn- thesis and verification [6, 7, 8, 9]. We recently developed a portable parallel algorithm for the transduction method [4] of logic synthesis [10], and results of the parallel algorithm were presented for a variety of parallel plat- forms. Even though we obtained reasonably good speedups using that algorithm, the original sequential algorithm using the trans- duction method has very large run times. The more popular logic This research was supported in part by the National Science Foundation under grant MIP-9320854, the Semiconductor Research Corporation un- der grant SRC 94-DP-109, and the Advanced Research Projects Agency under contract DAA-H04-94-G-0273 administered by the Army Research Office. synthesis algorithm is MIS-II, which is based on iterative factor- ing and simplification of nodes in a Boolean network. This algo- rithm forms the core of numerous university and industrial logic synthesis systems. A previous attempt to parallelize MIS-II re- sulted in poor speedups and significant loss in quality, because the MIS-II algorithm is inherently sequential in nature and ex- tremely hard to parallelize [7]. In this paper, we therefore present ProperMIS, a new paral- lel MIS-II based algorithm for logic synthesis that uses an asyn- chronous message-driven computing model with no synchroniz- ing barriers separating phases of parallel computation. Using the ProperCAD II system, the algorithm is portable across a wide va- riety of parallel architectures. 2 ProperCAD II Overview Much of the work in parallel CAD reported to date suffers from a major limitation in that these proposed parallel algorithms are designed with a specific underlying architecture in mind. As a re- sult, these applications perform poorly on architectures other than the one for which they were designed. Just as importantly, incom- patibilities in programming environments make it difficult to port these programs across different parallel architectures. This limi- tation has serious consequences, since a parallel algorithm needs to be developed afresh for every target MIMD architecture. One of the primary concerns of the ProperCAD project [11] is to address this portability problem by designing algorithms to run on a range of parallel machines including shared memory multi- processors, distributed memory multicomputers, and networks of workstations. The ProperCAD approach to the design of parallel CAD algorithms is illustrated in Figure 1. A parallel algorithm is designed around an existing uniprocessor algorithm by identifying modules in the uniprocessor code and designing a well-defined in- terface between the parallel and sequential code. The project has undergone two distinct phases, the first of which, ProperCAD I, involved the use of the C-based Charm language and runtime system [12]. The second phase, Proper- CAD II [13, 14], entailed the creation of a C++ library which provided an object–oriented parallel interface based on the actor model of concurrent object–oriented computing. The ProperCAD II library provides the mechanisms necessary for parallel execution in through the use of a fundamental object called an actor [15]. An actor object consists of a thread of con- trol that communicates with other actors by sending messages, and all actor actions are in response to these messages. Specific actor