ORIGINAL PAPER An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications Prateek Kishor Verma 1 & Santosh Kumar Gupta 1 Received: 14 November 2019 /Accepted: 13 May 2020 # Springer Nature B.V. 2020 Abstract A small-signal radio-frequency (RF) parameters extraction model along with analog/RF and linearity distortion performance analysis are realized for virtually doped (VD) recessed source/drain dopingless junctionless transistor (Re S/D DLJLT) via 3-D device simulations. A simple and accurate RF non-quasi-static (NQS) model is developed to directly extract the extrinsic and intrinsic parasitic components through Y-parameters in OFF and ON-state respectively. Furthermore, direct comparison of DC, analog/RF, linearity figure of merits (FOMs), and Y-parameter extractions are made with recessed source/drain junction tran- sistor (Re S/D JT) with identical threshold voltage (V th ) and device dimensions at GHz frequency range. Virtual doping, due to charge-plasma (CP) concept, provides N + source/drain (S/D) regions by choosing a most convenient metal work function (WF = 3.9 eV; Hafnium) at S/D. Re S/D provides reduced series resistance without an increase in gate-drain Miller capacitance leading to improved drive current. In addition, the present device uses an intrinsic channel and does not require to be doped at S/D resulting in dopingless junctionless transistor (DLJLT). For both devices, gate length (L) is taken as 30 nm, which separated into control gate (L 1 ) and screen gate (L 2 ) and 3-D simulations are carried out by varying control to screen gate length ratios (CSLR) to obtain optimum results. Obtained results disclose that Re S/D DLJLT provides considerably improved performances in terms of DC, analog/RF, linearity, transient, and small-signal admittance parameters over Re S/D JT due to improved drive current and reduced short channel effects (SCEs). Accordingly, for high-performance RF applications, Re S/D DLJLT may be preferred over Re S/D JT due to significantly enhanced cut-off frequency (up to 0.399 THz) and maximum oscillation frequency (up to 1.226 THz). Keywords Small-signal NQS model . Y-parameters . Re S/D . Virtually doped . Charge-plasma . RF applications . Linearity 1 Introduction In nano-scale regime, continuous shrinkage of the transistor’s dimensions impending the scaling limits of planer Metal- Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs) [1]. Due to extreme scaling, SCEs and OFF-state leakage cur- rents (I OFF ) are increased in short channel MOSFETs due to reduced gate control over the channel region [2]. Ultra-Thin- Box (UTB) Silicon-on-Insulator (SOI) MOSFETs is a better choice over planner MOSFETs due to their improved perfor- mances with some limitations. In UTB SOI MOSFETs, due to ultrathin S/D region, a high series S/D resistance is achieved, resulting in reduced drive current (I ON )[2, 3]. To reducing the series resistance, two main techniques, i.e., elevated S/D [4] and recessed S/D [5], have been reported earlier. Elevated S/D reduces the series resistance but increases the gate-drain Miller capacitance. The Re S/D offers more reduction in series resistance over elevated S/D without affecting the Miller ca- pacitance. This advantage offers better agreement between series resistance and Miller capacitance [5, 6]. Analog/RF performance evaluation of fully-depleted Re S/D SOI junction-based transistor has been previously reported [7]. In short-channel MOSFETs, forming a highly confined p-n * Prateek Kishor Verma prateek.kishor05@gmail.com Santosh Kumar Gupta skg@mnnit.ac.in 1 Param Lab, Electronics and Communication Engineering Department, MNNIT Allahabad, Prayagraj 211004, India Silicon https://doi.org/10.1007/s12633-020-00518-x