A Partitioning Methodology for BDD-Based Verification Debashis Sahoo 1 , Subramanian Iyer 2 , Jawahar Jain 3 , Christian Stangier 3 , Amit Narayan, David L. Dill 1 , and E. Allen Emerson 2 1 Stanford University, Stanford CA 94305, USA 2 University of Texas at Austin, Austin, TX 78712, USA 3 Fujitsu Labs of America, Sunnyvale, CA 94085, USA Abstract. The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this pa- per we advocate a methodology to handle this problem based on state space partitioning of functions as well as relations. We investigate the key questions of how to perform partitioning in reachability based veri- fication and provide suitable algorithms. We also address the problem of instability of BDD-based verification by automatically picking the best configuration from different short traces of the reachability computation. Our approach drastically decreases verification time, often by orders of magnitude. 1 Introduction Verification and synthesis of sequential circuits require efficient techniques to represent and analyze the state space of the design under consideration [6, 13]. It is well known that in sequential circuits the number of reachable states can be exponential in the number of state elements present in the circuit. A pop- ular approach to deal with this state explosion problem consists of implicitly representing and manipulating functions using Reduced Ordered Binary Deci- sion Diagrams (OBDDs) [2]. Though often efficient, there are cases, where the OBDD representation is not compact. Unfortunately, some practical applica- tion areas seem to exhibit this worst case complexity frequently. To overcome this problem of explosive memory requirements, the use of Partitioned-OBDDs (POBDDs) has been suggested [9]. By partitioning the state space into disjoint subspaces, and representing as well as processing all functions in each subspace independently of other subspaces, efficiency in time and space can be obtained. The partitioned reachability techniques suggested in [11] do not sufficiently address the practical issues involved with partitioning, and as a result do not scale well on many difficult circuits. In [8], dynamically partitioned OBDDs were introduced as a capable data structure that extend the usefulness of POBDDs for reachability and model checking. In this paper, we address the various issues related to partitioning, including but not limited to data structure issues, and demonstrate techniques that perform better than OBDDs as well as classical A.J. Hu and A.K. Martin (Eds.): FMCAD 2004, LNCS 3312, pp. 399–413, 2004. c  Springer-Verlag Berlin Heidelberg 2004