* Corresponding author. INTEGRATION, the VLSI journal 25 (1998) 1 — 16 VLSI design in the 3rd dimension Stephen Strickland*, Erhan Ergin, David R. Kaeli, Paul Zavracky Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA Abstract Recently, the need for increased circuit complexity has outpaced our ability to perform efficient routing and placement, while still maintaining small die sizes. Part of this problem can be attributed to the limits imposed by designing in two dimensions. Three-dimensional VLSI circuits, obtainable through using a transferred thin-film process, can provide a path for realizing complete structures, while reducing route lengths and die sizes. In this paper we report on our new three-dimensional design technology, devices which we have fabricated, and our move to an automated 3-D design path using Cadence and Synopsys design tools. We present both discussion of functional 3-D devices, and on-going work on VLSI design tools and the implementation of a 3-D microproces- sor.  1998 Elsevier Science B.V. All rights reserved. Keywords: 3-D microelectronics; VLSI CAD; Commercial tools; Layout and routing 1. Introduction The desire for increased circuit complexity is currently pushing two-dimensional (2-D) VLSI technology to its limits, causing problems such as large die sizes and non-negligible delays introduced by long power rails and data busses. Because of this, several schemes have been suggested to minimize the effects of interconnects on circuit performance. Some of these schemes include: 1. exploiting performance-driven placement and routing [1—5], 2. utilizing multiple interconnect layers [6], 3. providing interconnect scaling [7], 4. using interconnect materials with very low resistivity [8], and 5. using better interlayer dielectrics with low permittivity [8]. 0167-9260/98/$19.00  1998 Elsevier Science B.V. All rights reserved. PII: S 0 1 6 7 - 9 2 6 0 ( 9 8 ) 0 0 0 0 6 - 6