International Journal of Signal Processing, Image Processing and Pattern Recognition Vol.6, No.5 (2013), pp.333-342 http://dx.doi.org/10.14257/ijsip.2013.6.5.29 ISSN: 2005-4254 IJSIP Copyright ⓒ 2013 SERSC Robust Automatic Speech recognition System Implemented in a Hybrid Design DSP-FPGA Ali Aldahoud * , Hamza Atoui and Mohamed Fezari * Al-Zaytoonah University of Jordan, Amman, Jordan Badji Mokhtar Annaba University Faculty of Engineering, BP:12, Annaba, ALGERIA aldahoud@zuj.edu.jo, Hamza.atoui@gmail.com,mohamed.fezari@uwe.ac.uk, Abstract The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal pre-processing, feature selection and optimization, models construction and finally classification phase are necessary. LMS filter algorithm that contains more parallelism and more MACs (multiply and Accumulate) operations is implemented on FPGA Virtex 5 by Xilings , MFCCs features extraction and DTW( dynamic time wrapping ) method is used as a classifier. Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing MAC resources between two operation phases: computation of output filter and updating LMS filter coefficients. The paper also provides a hardware solution of the filter with detailed description of asynchronous interface of FPGA circuit and TMS320C6713-EMIF component. The results of simulation shows an improvement in time computation and by optimizing the implementation on the FPGA a gain in space consumption is obtained. Keywords: Configurable computing machines, FPGA-DSP hybrid Design, noise cancellation, LMS Filter Algorithm, speech recognition 1. Introduction Configurable computing machines (CCMs) bridge the gap between application specific integrated circuits (ASICs) and general-purpose microprocessors. They retain the flexibility of microprocessors while providing speed and power consumption more comparable to ASICs. CCMs represent a powerful alternative for certain applications, particularly communication systems. Speech processing in human-machine communication needs real- time processing; the utility of using faster and dedicated microprocessors is an obligation. Digital signal processors (DSPs) often lack the necessary speed to implement these algorithms, and additionally have higher power consumption—a significant drawback for embedded applications. Field programmable gate arrays (FPGAs) are the flexible computational resource in most mainstream CCMs. FPGAs consist of simple computational units called combinational logic blocks (CLBs) linked by a configurable connective mesh. While FPGAs are extremely versatile, they have a significant drawback as a software radio platform: long reconfiguration times. To reduce the hardware needs for a given application—consequently reducing cost and power consumption—it is desirable that platforms support runtime reconfiguration.