Journal of Integrated Circuits and Systems, vol. 16, n. 3, 2021 1 Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions Carlos J. Gonz ´ alez 1 , Diego N. Machado 2 , Rafael G. Vaz 3 , Alexis C. Vilas Bˆ oas 4 , Odair L. Gonc ¸alez 3 , Helmut Puchner 5 , Nemitala Added 6 , Eduardo L. A. Macchione 6 , Vitor A. P. Aguiar 6 , Fernanda L. Kastensmidt 1 , Nilberto H. Medina 6 , Marcilei A. Guazzelli 7 , Tiago R. Balen 1 1 Graduate Program in Microelectronics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil. 2 Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre, Brazil. 3 Aeronautics Science and Technology Department, Institute for Advance Studies, S˜ ao Jos´ e dos Campos, Brazil. 4 Electrical Engineering Department, FEI University Center, S˜ ao Bernardo do Campo, Brazil. 5 Infineon Memory Solution, San Jose, USA. 6 Institute of Physics, University of S ˜ ao Paulo, S ˜ ao Paulo, Brazil. 7 Physics Department, FEI University Center, S˜ ao Bernardo do Campo, Brazil. e-mail: cjgaguilera@inf.ufrgs.br Abstract— This work presents results of three distinct radiation tests performed upon a fault tolerant data acqui- sition system comprising a design diversity redundancy technique. The first and second experiments are Total Ion- izing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based vot- ers, besides additional software and hardware resources used for controlling, monitoring and memory manage- ment. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the process- ing unit present a higher criticality. Critical errors occur- ring in one of the voters were also observed. A second heavy ion campaign was then carried out to investigate the voters reliability, comparing the the dynamic cross sec- tion of three different software-based voter schemes im- plemented in the considered PSoC. Index Terms— Design Diversity Redundancy; Mixed- Signal; Radiation; Single Events; Soft Errors; Fault Toler- ance; Analog-to-Digital Converters; Programmable device; PSoC. I. I NTRODUCTION Ionizing radiation effects in integrated circuits (ICs) significantly affects the reliability of electronic systems exposed to such environmental condition. Although soft errors caused by Single Event Effects (SEEs) in modern electronics configure a significant reliability problem [1], [2], and may even be destructive in some cases [3], Total Ionizing Dose (TID) effects are determi- nant to the system lifetime, when operating in radia- tion environments [4]. Electronic systems applied to control, instrumenta- tion and communication tasks comprise mixed-signal interfaces that include Analog-to-Digital Converters (ADCs). These circuits are crucial in satellites, space- crafts and data acquisition systems of nuclear facilities and particle accelerators, for instance. Therefore, as im- portant as the correct functioning of computing units and digital system parts, is the reliability of analog-to- digital (AD) and digital-to-analog (DA) system inter- faces. Examples of works in which reliability to radia- tion effects and mitigation techniques were evaluated in such blocks can be found in [5, 6, 7, 8, 9, 10, 11]. In a previous work of our research group a fault- tolerant data acquisition system (DAS) was proposed to cope with radiation effects and other environmen- tal degradation sources [7, 12, 13, 14]. The sys- tem was designed and programmed in a Commercial Programmable System-on-Chip (PSoC) from Cypress Semiconductor (now Infineon Technologies) [15] fabri- cated in a 130 nm CMOS process. The adopted fault tolerance strategy is based on diversity redundancy, with hardware and time redundancy, in a way that the DAS is composed of three ADCs operating in paral- lel and two voters. In previous works, we firstly per- formed an intensive fault injection campaign, by us- ing a fault injection system based on a pseudo-random number generator implemented in an auxiliary board, to select the memory and bit positions, to insert the faults, and software interruption to perform the bit-flip injection routine [16]. In fact, a PSoC device was already tested under fault injection in a related work [17]. However, the experi- ment was directed to a device from the first generation of the PSoC family (comprising a simple 8-bit proces- sor). The target application in that work was purely digital (matrix multiplication), to which no mitigation technique was applied. In the current work, the studied device pertains to the third generation of PSoC family from Cypress Semiconductor (comprising a 32 bit ARM processor). Additionally, the application is a fault tolerant mixed- signal system based on design diversity, comprising Digital Object Identifier 10.29292/jics.v16i3.567