The role of the interfaces in the 1/f noise of MOSFETs with high-k gate stacks F. Crupi 1 , P. Magnone 1 , E. Simoen 2 , A. Mercha 2 , L. Pantisano 2 , G. Giusi 1 , C. Pace 1 and C. Claeys 2,3 1 DEIS, Università della Calabria, Italy 2 IMEC, Belgium 3 EE Depart., KU Leuven, Belgium This paper focuses on the impact of the gate and substrate interfaces on the 1/f noise of the drain and the gate current of MOSFETs with high-k gate stacks. Three case studies are critically discussed to highlight the key role played by both interfaces in the 1/f noise. First, we show how a sub-monolayer of HfO 2 sandwiched between SiON gate dielectric and poly-Si gate significantly increases the 1/f noise. The second case study indicates that a LaO cap on top of HfSiON significantly decreases the 1/f noise. The third experiment shows that the 1/f noise can be reduced by increasing the thickness of a SiO 2 interfacial layer sandwiched between the substrate interface and the HfO 2 layer. Introduction Hafnium-based gate dielectrics have been successfully introduced into a CMOS process for the 45 nm technological node [1-15]. Several other high-k materials, such as Lanthanum-based dielectrics, are currently under investigation to further extend the CMOS scaling [16]. The introduction of these alternative materials is accompanied by a significant increase of the drain and gate current 1/f noise [17-21]. The origin of this noise increase is the larger defect density of these materials with respect to conventional thermally grown silicon dioxide (SiO 2 ) or nitrided silicon oxide (SiON) gate dielectrics. Depending on the chemistry for dielectrics and gate electrodes considered, these defects may not be uniformly distributed in the dielectric volume but larger close to gate and / or substrate interfaces. These defects can act as a source of fluctuations in: i) the number and / or the mobility of the charge carriers in the channel, thus increasing the 1/f noise of the drain current and ii) the tunneling probability of the charge carriers through the gate dielectrics, thus increasing the 1/f noise of the gate current. In addition to the noise increase, the higher defect density observed in high-k gate stacks causes threshold voltage shift [5], negative and positive bias-temperature instability [8,9], mobility reduction [10-13], trap-assisted tunneling and stress-induced leakage current (SILC) [4]. While the 1/f noise measurements of the drain current have been extensively used for sensing the defects in the gate dielectrics [17-18, 22-27], only a few works have been devoted to the use of the gate current 1/f noise for the same purpose [19-21, 28-30]. The main advantage of using gate current 1/f noise as diagnostic tool for assessing the quality of the gate stack in MOS structures is its intrinsic immunity to the large gate leakage, which corrupts the accuracy of the other standard techniques, such as a combination of high frequency and quasi-static C-V [31], charge pumping [32,33], and drain noise measurements [22-27]. ECS Transactions, 19 (2) 87-99 (2009) 10.1149/1.3122087 ©The Electrochemical Society 87 Downloaded 17 Jun 2011 to 146.103.254.11. Redistribution subject to ECS license or copyright; see http://www.ecsdl.org/terms_use.jsp