International Journal of Advanced Engineering Research and Science (IJAERS) [Vol-3, Issue-9, Sept- 2016] https://dx.doi.org/10.22161/ijaers ISSN: 2349-6495(P) | 2456-1908(O) www.ijaers.com Page | 42 Analysis of Phenomenon at Quantum Capacitance Limit of SNWFET using FETToy Manish Mishra 1 , Abhinav Shukla 2 , UN Tripathi 3 , Harsha Gupta 4 1,2 Department of Electronics, DDU Gorakhpur University, Gorakhpur, Uttar Pradesh, India 3 Department of Computer Science, DDU Gorakhpur University, Gorakhpur, Uttar Pradesh, India 4 Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Sector 128, Noida, Uttar Pradesh, India Abstract— In The proposed paper several interesting phenomenon that happens at Quantum Conductance Limit (QCL) like transconductance of One Dimensional-Silicon Nano Wire Field Effect Transistor (1D-SNWFET), mobile electron density and injection velocity is studied and simulated using Fettoy simulation tool. The selected gate material in silicon nanowire field effect transistor is SiO 2 with K=3.9 and HFO 2 with K=20. A coaxial SNWFET is simulated and the results illustrate the essential physics and peculiarities of 1D nanowire FETs, such as the saturation of channel conductance at full degenerate limit and the saturation of transconductance at the quantum capacitance limit and the full degenerate limit. Keywords— SNWFET, Quantum Capacitance, Non- degenerate, Full-degenerate, SiO 2 , HFO 2 , FETToy. I. INTRODUCTION A nanowire is a nanostructure with diameter of the order of a nanometer (10 -9 meter). Alternatively nanowire can be defined as structures that have a thickness or diameter constrained to tens of nanometer or less and an unconstrained length. Typically, nanowires exhibits aspect ratio (length to width ratio) of 1000 or more. As such they are often referred to as one dimensional material and have many interesting properties that are not seen in bulk or 3D materials. This is because electrons in nanowire are quantum contained laterally and thus occupy energy levels that are different from traditionally continuum of energy levels or band found in bulk material[1]. Many different type of nanowires exist some of them are: (a) Metallic (Ni, Pt, An) (b) Insulating (SiO 2 , TiO 2 ) (c) Semiconducting (Si, In, GaN) [2] In this paper our interest is to simulate SNWFET with different device parameters and to look its peculiar nature. II. QUANTUM CAPACITANCE The mobile charge Q TOP depends on the potential at the top of the barrier U SCF . To describe this relation a non-linear quantum or semiconductor capacitance [3-6] can be defined as: C Q ≡ │     │ (1) Under high drain bias: Q TOP = -qn + = (-qN 1D /2) -1/2 (ղ F ) (2) So C Q = │     │ = │         │ =            (  )   According to the properties of the Fermi integral, the quantum capacitance C Q is obtained as: C Q =          (  )   = M     ∗ Пℏ     exp (  ) (3) Equation (3) is for Non-degenerate case. C Q =       Γ(/)   /   = M      ∗ "  ℏ      - 1/2 =M     ∗ П  ℏ  [$ % &(’(()&  )] (4) Above equation (4) is for full generate case, It is implied from equation (3) and (4) that the quantum capacitance increased with the gate voltage under low gate bias ( Non- degenerate) while it decreases with the gate voltage under high gate bias ( full degenerate ). This effect is clearly illustrated in fig 1, i.e. C Q vs. V GS plots for simulated SNWFET with (a) SiO 2 layer and (b) HFO 2 layer. When the gate insulator capacitance is significantly larger than the quantum capacitance (C Q /C G →0), the FET works at the