Low-Cost Diagnostic Pattern Generation and Evaluation Procedures for Noise-Related Failures Junxia Ma 1 , Nisar Ahmed 2 and Mohammad Tehranipoor 1 1 ECE Department, University of Connecticut, Storrs, CT, 06269 1 {junxia, tehrani}@engr.uconn.edu 2 Texas Instruments, Dallas, TX, 75243, n-ahmed@ti.com ABSTRACT As technology feature geometries shrink, failures caused by signal integrity issues have become prominent during test. To avoid the time consuming silicon inspection and reduce the engineering cost and effort for failure analysis, a fast and cost-effective diagnostic flow is proposed in this paper. The flow targets delay faults and can be used to (1) identify noise-related failures with a quiet pattern and (2) evaluate the failed pattern in terms of its noise-induced delay to help identify the root cause of failure. A novel procedure is developed to generate a quiet pattern to help differentiate sources of the failure. The quiet pattern targets the same physical defects as the failed pattern but offers much lower noises level. A pattern evaluation procedure is used to evaluate the noise-induced delay. The proposed procedures are implemented on ITC’99 b19 benchmark. Simulation results demonstrate the effectiveness of the proposed procedure in identifying the failure mechanism. The noise-induced path delay for both failed patterns and diagnostic quiet patterns are thoroughly evaluated. Keywords: Diagnosis, Delay Test, Crosstalk, Power Supply Noise, Quiet Pattern Generation. I. I NTRODUCTION As technology advances, it is vitally important for the semiconduc- tor industry to shorten the time-to-market and deal with yield, yield loss and escape more effectively. Fast and effective fault diagnosis techniques are essential to help improve the yield and product quality [1]. Industry surveys show that more than 70% of all IC designs need one or more respins [2], in spite of the large amount of resources devoted to design, validation and verification at every step. Fast, accurate and low-cost diagnosis is always in need to find the root cause of the failures and provide feedback to the designers. Timing failures are often the result of a combination of weak points in a design and silicon abnormalities [2], which reduce the noise immunity of the design and expose it to signal integrity (SI) issues. Design weak points are due to imperfect design, i.e., poor power planning, inadequate power vias, and long parallel interconnects; while silicon abnormalities are caused by manufacture errors, i.e., missing vias, via voids, resistive opens or vias for power/ground lines and signal interconnects. A poor power planning, resistive open power lines/vias, or missing power vias can incur on-chip power droop for some test vectors. The power droop can impact a gate(s) on a critical path and may cause timing failure. Crosstalk noises introduced by large parasitic coupling capacitances between long parallel interconnects can also impact the path delay. Such failures are switching dependent and may only be excited with certain test vectors as inputs. Mostly small-delay defects (SDDs) manifest such problems and the accumulative SDDs cause timing * This work is supported by National Science Foundation grant CCF- 0811632. failures. Currently the commercial diagnosis tools are noise unaware. If a test part fails due to excessive power supply noise and/or crosstalk noise, with sufficient fail/pass test patterns counts, the tool can report a list of suspect pins for corresponding failure model (i.e., slow-to- rise/fall faults). However, it has no information of the failure reason for the suspects. Although for pure IR-drop failures, changing test supply voltage can help find the failure reason; it does not help for crosstalk noise related failures, because crosstalk noise has no direct connection with supply voltage. Since no physical defects can be observed under microscope for noise related failures, it is vain to check the suspects under microscope. Besides, laser-based timing analysis [3] can only be performed on device’s active diffusion regions; while interconnects usually go through multiple metal layers, so it is very time-consuming and most of the time impossible for failure analysis engineers to inspect the silicon to identify the root cause. Diagnosis for physical defects such as stuck-at, bridge, short and delay faults have been extensively investigated in the past decade. There are many sophisticated tools and procedures that can effectively point to the location of physical defects based on the collected failure log from tester [4] [5]. There has been less work devoted to developing effective procedures to address noise-related failures. In [6], Killpack et al. discussed the causes of at-speed failures in microprocessors. The relative importance of IR-drop and crosstalk compared with defect issues in observed speed-path failures was addressed. Saxena et al. presented a case study for an IR-drop induced failure in scan-based at-speed test [7]. Mehta et al. proposed a methodology to diagnose delay defects in presence of crosstalk [8]. A test pattern generation method to identify IR-drop failures during launch-off-shift (LOS) test was proposed in [9]. It minimizes launch and capture mode transitions in LOS test to reduce test mode IR- drop; however, it does not take into account crosstalk-induced delay. In practice, Shmoo plots developed based on sweeping the voltage and frequency during test pattern application are used for failure root cause analysis. However, changing frequency and voltage will only change the voltage drop characteristics and other sources of noise is neglected. For instance, as technology scales, crosstalk-induced delay could be as much as IR-drop induced delay in the circuit. Motivated by the reasons presented above, we propose fast, low- cost diagnostic pattern generation and evaluation procedures that are applicable to both transition delay faults (TDF) and path delay faults (PDF), and can be used in both launch-off-shift (LOS) and launch- off-capture (LOC) test schemes. It avoids the time consuming silicon inspection and reduces the engineering cost and effort in failure analysis. The proposed diagnostic procedures can be used to: (1) Identify the noise caused failures; (2) Evaluate the noise strength for the failed patterns; (3) Grade patterns during path delay fault testing to ensure selection of high quality patterns to improve the quality of manufacturing test and minimize escape. The rest of the paper is organized as follows. In Section II, an example is used to discuss the problem and application targeted by 2011 29th IEEE VLSI Test Symposium 978-1-61284-656-9/11/$26.00 ©2011 IEEE 309