Contents lists available at ScienceDirect INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs Bibhas Ghoshal a, ⁎ , Chittaranjan Mandal b , Indranil Sengupta b a Department of Information Technology, Indian Institute of Information Technology, Allahabad 211012, India b Department of Computer Science and Engineering, IIT Kharagpur, Kharagpur, India ARTICLE INFO Keywords: DRAM Permanent faults Transparent test March test Refresh-reuse ABSTRACT In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re- using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead. Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware. 1. Introduction The run-time faults which occur in Dynamic Random Access Memories (DRAMs) are either transient or intermittent [1]. A lot of research has been devoted in devising efficient run time fault detection techniques for DRAMs. The detection techniques of these run-time faults reported in literature have mainly focussed on detection of transient faults (soft errors). However, for deeply scaled CMOS based DRAMs, the occasional run-time faults in DRAMs which are a result of physical effects such as environmental susceptibility, aging and low supply voltage, are intermittent faults [2]. These intermittent faults usually exhibit a relatively high occurrence rate and eventually tend to become permanent [2]. Moreover, wearout of DRAM can also cause intermittent faults to become frequent enough to be classified as permanent [3]. Studies on DRAM failures in field ([4–6]) provided evidence that DRAMs experience both transient (soft) faults and permanent (hard) faults in field. Thus, for a DRAM based system which develops both soft errors and hard faults during in-field operation, using only software based detection mechanisms (memory diagnostic software programs used to check for memory failures on a computer) such as ECC [7], Chipkill [8] or memory scrubbers [9] may not be sufficient as suggested by the results in [10]. Sridharan et al. in [10] reported that a commonly used ECC technique such as SEC-DED ECC results in undetected errors (causing silent data corruption) at a rate of up to 20 FIT per DRAM device (unacceptably high rate for many enterprise data centers and high- performance computing systems), thus making it poorly suited to modern DRAM subsystems. Memory scrubbing with ECC may be an alternative. However, there are a few drawbacks in implementing scrubbers (in both hardware and software) for DRAM testing as mentioned in [11]. Implementing scrubber as state machine in memory controller increases the hardware complexity and causes performance penalty as memory becomes inaccessible during the scrubbing period. Software implementa- tion requires generation of interrupt to activate a firmware which executes on the processor to perform scrubbing. However, due to limited number of interrupt request signals or vectors in some systems, an interrupt for scrubbing often is not available. As result, the software based solution is often infeasable. Thus, for a system which develops both soft errors and hard faults during in-field operation, the most preferred solution is to apply a http://dx.doi.org/10.1016/j.vlsi.2017.06.011 Received 9 February 2017; Received in revised form 21 April 2017; Accepted 24 June 2017 ⁎ Corresponding author. E-mail addresses: bibhas.ghoshal@iiita.ac.in (B. Ghoshal), chitta@iitkgp.ac.in (C. Mandal), isg@iitkgp.ac.in (I. Sengupta). INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx 0167-9260/ © 2017 Elsevier B.V. All rights reserved. Please cite this article as: Ghoshal, B., INTEGRATION the VLSI journal (2017), http://dx.doi.org/10.1016/j.vlsi.2017.06.011