IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011 2293 Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study Xingsheng Wang, Andrew R. Brown, Member, IEEE, Niza Idris, Stanislav Markov, Member, IEEE, Gareth Roy, and Asen Asenov, Fellow, IEEE Abstract—This paper presents a comprehensive full-scale three- dimensional simulation scaling study of the statistical threshold- voltage variability in bulk high-k/metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granular- ity (MGG) and corresponding workfunction-induced threshold- voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distrib- ution when the metal grain size cannot be adequately controlled. Index Terms—Granularity, metal gate, MOSFETs, scaling, variability, workfunction. I. I NTRODUCTION T HE semiconductor industry relies on continuous MOSFET scaling to deliver ever-increasing functionality and performance in digital applications. With the introduction of high-k/metal gate stack at the 45-nm technology generation [1], the projected lifetime for bulk MOSFETs was effectively extended to 14-nm physical gate length for high- performance transistors [2]. The high-κ/metal gate stack enables further reduction of equivalent oxide thickness (EOT) without compromising gate leakage [3]. This improves the electrostatic integrity and delivers the required performance for a conventional (bulk) MOSFET, which remains the workhorse Manuscript received October 4, 2010; accepted April 22, 2011. Date of publication May 31, 2011; date of current version July 22, 2011. This work was supported in part by the EU ENIAC Joint Undertaking project “MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems” (MODERN) and in part by the EU FP7 project “Terascale reliable adaptive memory systems” (TRAMS). The work of X. Wang was supported in part by the U.K. Overseas Research Students Awards Scheme. The review of this paper was arranged by Editor M. D. Giles. X. Wang, A. R. Brown, N. Idris, S. Markov, and G. Roy are with the Device Modelling Group, School of Engineering, University of Glasgow, G12 8LT Glasgow, U.K. (e-mail: Xingsheng.Wang@glasgow.ac.uk). A. Asenov is with the Device Modeling Group, School of Engineering, University of Glasgow, G12 8LT Glasgow, U.K., and also with Gold Standard Simulations Ltd., G12 8LT Glasgow, U.K. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2149531 of the semiconductor industry [4], [5]. However, further scaling faces an increasing number of technological and physical challenges, among which statistical variability has become one of the major sources of concern for the industry [6], [7]. Variability degrades the circuit and system performance and increases the power dissipation in contemporary chips. The potential sources of statistical variability, which are already well studied, include random discrete doping (RDD) [8]–[18], line edge roughness (LER) [19]–[24], poly-silicon granularity [25]–[27], and random grain orientation in the high-κ di- electric [28]. The reduction of EOT enabled by the deployment of high-κ dielectric stacks allows for a significant reduction in the vari- ability of bulk MOSFETs, since the standard deviation of the threshold voltage due to RDD (being by far the dominant factor) is proportional to the EOT [6], [31]. However, the presence of a metal gate in place of a poly-Si gate renders a new variability source [32]. The metal gate morphology can be amorphous or polycrys- talline, with grains varying in size (in the range of 5–50 nm) and orientation, depending on the fabrication conditions [33]–[35]. Metal gate granularity (MGG) is more difficult to control when using a gate-first technology, where postmetallization annealing can lead to metal gate crystallisation [5], [36]. The variation in the metal grain crystal orientation results in the variation in the workfunction due to the different surface densities of polarization charges [4], [5], [37]. The grain workfunction variations lead to corresponding local threshold variations in the gate region. This results in statistical variability in device char- acteristics dependent on the size, orientation, and workfunction of the grains forming the gate of a transistor. The impact of MGG on threshold-voltage variability has been previously investigated using analytical models [38]–[40] or simulations assuming square grains [41]–[43]. However, the problem requires more advanced physical and statisti- cal treatments, as has been demonstrated by statistical three- dimensional (3-D) device simulations of a bulk MOSFET with 32-nm gate length [44]. In this case, the threshold-voltage distribution is radically non-Gaussian due to the presence of MGG, particularly when the average grain size is on the same order as the gate area. Therefore, it is very difficult to project the magnitude of threshold-voltage variability in future technology generations. To our best knowledge, there is no comprehensive and realistic study of the impact of MGG in scaled technologies 0018-9383/$26.00 © 2011 IEEE