Journal of Electrostatics 107 (2020) 103459 Available online 18 May 2020 0304-3886/© 2020 Published by Elsevier B.V. A parasitic impedance effect study using a discharge probe for FICBE testing based on CDM waveform verifcation ☆ S. Pimpakun a , S. Chumpen a , S. Plong-ngooluam b , S.H. Voldman c , C. Sa-ngiamsak a, * a Electrical Engineering Department, Faculty of Engineering, Khon Kaen University, Khon Kaen, 40002, Thailand b Western Digital (Thailand) Company Limited, 140 Moo 2, BangPa-in Industrial Estate, Klongjig, Bangpa-in, Ayutthaya, 13160, Thailand c LLC, Lake Placid, NY, 12946, USA A R T I C L E INFO Keywords: Charged board model Charged board event discharge probe Parasitic inductance ABSTRACT Field Induced Charged Board Events (FICBE) experiments were conducted. The waveforms were verifed using charged device model (CDM) standards. The discharge probe was constructed to determine the electrostatic discharge sensitivity of a PCB. The standard CDM current waveforms were used as a reference to ensure proper function of the discharge probe. The investigation revealed that a lower impedance of a pogo pin improved the sensitivity. The parallelizing of a pair of 2 Ω resistors reduced the parasitic inductance. Inclusion of a ferrite bead on the current sensing wires reduced the common mode noise. This test bench complies with standard CDM current waveforms. 1. Introduction Electrostatic discharge sensitive (ESDS) devices remain at risk when they are mounted onto printed circuit boards (PCB) and other assem- blies. The important reason for this study is due to a PCB has higher parasitic capacitance than that of electronic devices. PCB can become a higher energy storage for static charges. They can cause device failure or be harmed by electrostatic discharge (ESD) events. Many ESD failures in circuits and system assemblies occur at the PCB level, even though the device passed the standard CDM testing [1,2]. Some electronic manu- factures found that their ESDS devices had malfunctioned on production lines, at the fnal test process, after a chip was mounted onto the PCB [3]. The failures at that stage were classifed as electrical over stress (EOS) instead of the ESD failure due to a charged board event (CBE) [4–6]. Researchers [7] described that the statistical distribution of charged board event failures in electronic assembly environments were mostly ESD failure events. A charged board event was simulated by setting up the experiment with CDM frame of work. The induced-charged conductive board made a contact with another conductive object (victim) at different voltage potential. This results in electrostatic discharge as CBE. A CBE test was successfully replicated and described as a real-world CBE failure [2,4,8]. A feld-induced charged board event (FICBE) testing for PCB refers the CDM test method to classify the sensitivity of CBE. The current waveform of CBE has higher peak than that of CDM; hence PCB may require a lower ESD CBE sensitivity level for a large device and/or many power pins and ground pin [2]. Designing a test bench for CBE using CDM standard may not be straight forward, because the discharge path of CBE is more complex than that of CDM due to numerous power pins and ground pin of PCB occupied lower inductance and resistance on the discharge path. The complication of applying CDM standard testing upon CBE requires a thorough study on CBE test bench design. Another important key factor in CDM waveform verifcation is the discharge probe structure. The parasitic parameters in the discharge probe can distort the discharge current fowing in to the measurement apparatus. The discharge probe has three important considerations: the effect of the pogo pin, the type of resistive current sensor, and common mode noise reduction using ferrite beads. The pogo pin is frst consid- ered as an important part of a discharge probe. Researchers [10] described how the CDM waveform can be distorted based on the pogo pin diameter and length. The peak value of the discharge current could be increased using a larger pogo pin diameter. Alternatively, pogo pin ☆ This research has been supported by the Matching Fund, contract no. MSD60I0118 and PHD60I0051 between the Thailand Research Fund (TRF) and Western Digital (Thailand) Company Limited, under the Research and Researchers for Industries (RRI) project. This report presents the fndings of the researchers. The supporters do not necessarily always agree. * Corresponding author. E-mail addresses: sumatee.pimpakun@kkumail.com (S. Pimpakun), Csupaporn@kkumail.com (S. Chumpen), Sayan.Plong-ngoolaum@wdc.com (S. Plong- ngooluam), voldman@ieee.org (S.H. Voldman), chiranut@kku.ac.th (C. Sa-ngiamsak). Contents lists available at ScienceDirect Journal of Electrostatics journal homepage: http://www.elsevier.com/locate/elstat https://doi.org/10.1016/j.elstat.2020.103459 Received 24 November 2019; Received in revised form 31 January 2020; Accepted 31 March 2020