High Voltage P-Channel MOS Breakdown Voltage Instability During High Temperature Gate Stress Induced by Pre-Metal Nitride Layers G. Marchesi, J. Cambieri, A. Dundulachi, G. Pizzo, F. Pozzobon, M. Annese, A. Andreini, G. Croce STMicroelectronics, FTM R&D, Via C. Olivetti 2, 20041 Agrate Brianza (Milano) Italy Tel: +39-039-603-7205, Fax: +39-039-603-7410, giulio.marchesi@st.com Abstract— An anomalous Breakdown Voltage degradation has been observed during High Temperature Gate Stress (HTGS) test on 20 V Double Diffused Drain (DDD) P-channel device realized on a 0.18 μm High Voltage Gate (HVG) platform. The critical role played by the SALICIDE protection and BORDERLESS Nitride layers has been pointed out by dedicated process trials. I. INTRODUCTION Display Drivers ICs market is considered as a very fast growing segment both for Mobile applications and for Home Panel TV (Large Size) sets. Mobile segment is addressed with single chip solutions for the Display Drivers realized on advanced technology platform (0.18 μm [1], 0.13 μm [2]) including thick Gate oxide transistors for High Voltage Gate (HVG) operations. Large Size drivers’ ICs requirements are quite different. Several column drivers with multiple high voltage output circuitries are normally present on a Large Size display. Logic cores are limited in terms of gates number, two Gate oxides are normally used and voltage capability is limited to 20 V. A dedicated process option has been derived from [1] to proper fulfill these specific requirements: HVG8 Large Size (HVG8LS). Advanced CMOS features such as Shallow Trench Isolation (STI), dual flavored Gate, Cobalt SALICIDE and BORDERLESS contacts are shared with the similar 0.18 μm technology platform [1], [3]. p+ p+ p+ p+ n+ n+ Pfield Pfield PDDD PDDD SHVNWELL SHVNWELL p-/p+ Substrate p-/p+ Substrate p+ p+ p+ p+ n+ n+ Pfield Pfield PDDD PDDD SHVNWELL SHVNWELL p-/p+ Substrate p-/p+ Substrate (a) (b) Figure 1 - Cross section of 20V PMOS Drain Extension symmetric (a) and 20 V PMOS DDD for HVG8 LARGE SIZE option (b). Thin Gate Oxide for 1.8 V CMOS and Thick Gate Oxide, able to withstand more than 20 V, are embedded on this process. Drain Extension (DE) symmetric architecture (Figure 1a) is widely used to realize high voltage devices (up to 32/40 V) on thick Gate oxide. For Large Size Screen display drivers applications DE devices has not been considered as the optimum choice in terms of performances due to the following reasons: 1. Drain extension region below field oxide region leads to a larger on-state resistance (R on ); 2. The overlap between Gate and Drain leads to large Gate-Drain capacitance (C gd ) giving a lower cut-off frequency. Double Diffused Drain (DDD) symmetric architecture (Figure 1b) has therefore replaced Drain Extension one in HVG8 Large Size option: the reduced Gate/Drain overlap region together with the overall improvement of all the on- state parameters coming from the STI removal leads to a significant cut-off frequency increase for 20 V capable devices as shown in Table I. TABLE I. DIFFERENCES BETWEEN 20 V NMOS/PMOS DRAIN EXTENSION SYMMETRIC AND 20 V NMOS/PMOS DDD SYMMETRIC FOR HVG8 LARGE SIZE OPTION 20 V Drain Extension symmetric 20 V DDD symmetric R on ·W 20.5 ·mm (at VGS = 20V) 9.7 ·mm (at VGS = 20V) NMOS f t MAX 1.4 GHz (at VDS = 5V) 3.6 GHz (at VDS = 5V) R on ·W 50.7 ·mm (at VGS = -20V) 25.6 ·mm (at VGS = -20V) PMOS f t MAX 0.6 GHz (at VDS = -5V) 1.8 GHz (at VDS = -5V) 1-4244-1533-0/08/$25.00 ©2008 IEEE 275 Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC's May 18-22, 2008 Oralando, FL