Optimal Body Biasing for Maximizing Circuit Performance in 65nm CMOS Technology Farshad Moradi 1,3, Tuan Vu Caol, Dag T. Wislad I, Snor e Aunee, Hid Maoodi2, INaoelectronic goup, University of Oslo, Norway 2School of Engineering, Sa Fracisco State University, CA, USA 3Navik University College, Narvik, Norway ABSTRACT In thi paper, the efect of bod-biasing technique in 65nm CMOS technolog is investgaed The optmum bod volage in diferent process corer to get the mamum ON cu"ent is acquired using ST 65nm technolog. The efectveness of body biaing technique i investgated for sub- and super threshold dsigns We show tha for higher supply voltage, there is an optmum bod volage to ge the mamum petormance The results for some Fi-Fops are shown. Keyords Body-biasing, 65nm, nao-scale, sub-threshold I. INTRODUCTION Making energ efcient elecronic systems is currently becoming more and more importat. The demads for combining hig performance operation and long battery lifetime in portable ad wireless applications have strong implications on how to desig such systems. Te need for cost optimized solutions tageting lage volume applications results in combining all system components on one single chip usually referred to as a System on Chip (SOC). Such systems combine advaced R ad analog blocks in the font-end and anaogdigital interfacing circuitry with complex digital parts performing sigal processing, system control ad storage. I order to mae energ optimized solutions, all aspects must be taken into account. The introduction of intelligent power control ad efcient modulation methods h reduced the energy consumption of such systems sigifcantly. However some parts of the system may not be put in idle mode, especially those pats taking cae of the power control and monitoring trigger events for leaving idle mode. The fac tha these pars of the system are always on leaves a geat potential of saving energ by reducing the supply voltage and introducing new and innovative techniques a device-level. This paper is focusing on body-biasing techniques in order to fnd the optimum operating conditions for PMOS ad NMOS devices in deep subIicron technology. Body biasing techniques have been used to alter the MOS threshold voltage in order to either increase the speed or reduce leakage. According to theory ad in more conventional devices, forwad body biasing (FBB) reduces the threshold voltage while Reverse Body Biasing h the opposite efect. I deep submicron devices, the efec of these techniques is more complicated due to short channel efecs. This work is focusing on analyzing the efect of these techniques using a stadad 65nm CMOS process and to frther determine how to utilize FBB ad RBB to establish optimal operating conditions for digital circuitry targeting hig performance ad low energ operation. I order to predic the efect of FBB and RB both as a fnction of physical parameters, geometry ad temperaure, a aaytic approah combined with circuit simulations has been chosen to determine the physical origin of the observed behavior and the pracical consequences for circuit desig utilizing the subthreshold operating regime [I]-[3]. I secion II the body biasing technique is analyzed in detail along with simulaion results. I this section, the efect of body biaing in 65nm CMOS is investigated in detail. Section III shows some desig examples to show the efcacy of body-biasing technique. Secion N contains the conclusions. II. BODY BIASING TECHNIQUE I this section the efect of forward body biasing (FBB) ad reverse body biasing (RBB) techniques on the current throug NMOS ad PMOS devices a investigated. Body biasing is used to change the threshold voltage of trasistors governed by the following equaion: VT = VTO + (y,210FI + VSB - ,210FD (I) where ' is the body threshold paeter, V 1 is the threshold voltae in VSB=O, ad 0 F is the strong inversion surface potential which can be neglected compared with VSB for lower supply voltaes. Te threshold voltage equation may then be simplifed to this equaion: VT = VTO - yVBS (2) As observed fom this equaion, by increasing the body voltae (NMOS) relaive to the source voltage, the threshold voltage is decreaed ad then the current is increased, while in PMOS trasistors by increasing the body voltage (Reverse body bias), the threshold voltae is increased ad then the current is decreased [4]. By applying the RBB technique to NMOS devices, the source voltage is higer tha body voltage, so by increasing the source voltage, the threshold voltae increases ad then the current throug the NMOS is decreased. By utilizing reverse body biasing technique in NMOS devices, the threshold voltage decreases and as a result, the drain curent increaes which in tur improves the speed of the circuit. Theefore, the higest speed of the NMOS is expected to be when the body is connected to the maimum allowed forward body bia voltae. I the cae of a PMOS, when the body voltage is connected to lowest possible voltage, the threshold voltage is expected to be a its minimum, maimizing the ON current of the PMOS device. Te liIitation, however, is that the forward bias amount must be small enoug to prevent the junction diodes from turing on. This limits the forwad bias rage to be below the PN diode built-in potential, giving an acceptable forward bia range of about 500mV. Forwad bias h been shown not only to improve performance, but to also reduce short chanel efecs [5]. Reverse body bias is while the body to source is reversely biased. I this case, the current is expected to decrease due to negative body to source voltage. A. BodBiaing in Scaed Technolgies Body-Biasing efciency is diminished with technology scaling because of worsening SCE, especially when the taget V T value is low. I 65nm CMOS technology, body biasing technique has a diferent efect on NMOS ad PMOS devices compaed to older 978-1-61284-857-0/11/$26.00 ©2011 IEEE