A fabrication of a low-power low-noise neural recording ampliﬁer based on ﬂipped voltage follower Tamer Farouk a , Mohamed Dessouky b , Mohamed Elkhatib a, * a Department of Electronic Engineering, Military Technical College, Cairo, Egypt b ECE Department, Ain Shams University, Cairo, Egypt ABSTRACT In this work, a fabrication of low-voltage low-power and low-noise neural recording ampliﬁers are presented. An operational transconductance ampliﬁer (OTA) was built using the ﬂipped voltage follower (FVF). The low noise operation is achieved without increasing the bias current of the input transistors or decreasing the aspect ratio of the output transistors, which leads to large overdrive voltage. This proposed OTA is used to build a biopotential ampliﬁer using AC coupling technique to achieve one of the lowest noise efﬁciency factor (NEF) of 2.13. This bioampliﬁer is fabricated using UMC 130 nm CMOS process and the measurement results are obtained. The proposed OTA is also used to design a second biopotential ampliﬁer using active low-frequency suppression technique to achieve one of the lowest occupied area of 0.047 mm 2 while maintaining a reasonable Noise efﬁciency factor (NEF) of 4.27. The active low-frequency suppression technique is used to reject the DC offset voltage while preserving high input impedance and small area. The ﬁrst bioampliﬁer consumes 2.2 μA from 1 V supply voltage. The input-referred noise is 3.7 μV rms . The bandwidth (BW) ranges from 25 Hz to 9.9 kHz. The achieved noise efﬁciency factor (NEF) is 2.13. The dynamic range is 55 dB. It occupies a silicon area of 0.112 mm 2 . The second bioampliﬁer consumes 5.2 μW from 1 V supply voltage. The input-referred noise is 4.7 μVrms. The BW ranges from 110 Hz to 9.7 kHz. The achieved NEF is 4.27. It occupies an area of 0.047 mm 2 . 1. Introduction Neural-recording systems are used to sense the brain electrical signal [1–6]. Scientists found that the neural signal measured from many neu- rons in the brain is related to the intended limb movements [7,8]. Therefore the brain machine interfaces (BMI) could be made to help paralyzed patient to control a computer cursor by thoughts. The neural signal ampliﬁer is a crucial part of the brain machine in- terfaces. The neural signal is very week (10–500 μV) [9]. Therefore the ﬁrst stage of the neural recording circuits is the bioampliﬁer. Low-power operation is essential in neural recording applications to minimize the heat dissipation and maximize battery life. In this paper, despite the low noise operation is achieved, the input bias current has not been increased. In addition, the aspect ratio of the output transistors has not been decreased which leads to large overdrive voltage. The proposed OTA designed using the proposed gm-cell operates under a 1 V supply. This proposed OTA is used to build a biopotential ampliﬁer using AC coupling technique to achieve one of the lowest noise efﬁciency factor (NEF) of 2.13 as shown later in section 4. This energy- efﬁcient bioampliﬁer is designed, built, and tested in a 130 nm CMOS process. The proposed OTA is used to design a biopotential ampliﬁer using active low-frequency suppression to achieve one of the lowest occupied area of 0.047 mm2 while maintaining a reasonable NEF of 4.27 as shown later in section 4. 2. State of the art biopotential ampliﬁers There are many low noise, low power OTA circuits which have been designed. One of the most important OTA topologies is the one stage current mirror OTA designed by Harrison [10] used for neural recording preampliﬁer. The main source of the noise in his design is the input transistors, while the contribution of all other transistors to the input-referred noise is minimized. Gosselin in Ref. [11] designed a bioampliﬁer using active low-frequency suppression to reject DC offset voltage instead of ac coupling capacitors. This design achieves lower area consumption and higher input impedance because there is no need for the large input ac coupling capacitors. The modiﬁed folded cascode (FC) OTA with the current scaled in the input and output branches designed by Wattanapanitch [12], is consid- ered a power-efﬁcient design as the power consumption is reduced by decreasing the output branch quiescent current. It uses source degener- ation resistors, however, they increase the area and voltage head-room. The OTA designed by Qian [13] used the modiﬁed FC topology with * Corresponding author. E-mail addresses: tamerfarouk76@yahoo.com (T. Farouk), mohamed.dessouky@eng.asu.edu.eg (M. Dessouky), mohamed.m.elkhatib@ieee.org (M. Elkhatib). Contents lists available at ScienceDirect Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo https://doi.org/10.1016/j.mejo.2020.104817 Received 22 November 2019; Received in revised form 9 May 2020; Accepted 15 May 2020 Available online 21 May 2020 0026-2692/© 2020 Elsevier Ltd. All rights reserved. Microelectronics Journal 101 (2020) 104817