Contents lists available at ScienceDirect Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp Advanced processing for mobility improvement in 4H-SiC MOSFETs: A review Maria Cabello ⁎ , Victor Soler, Gemma Rius, Josep Montserrat, José Rebollo, Philippe Godignon Centro Nacional de Microelectrónica (CNM-CSIC) Campus UAB, 08193 Cerdanyola, Barcelona, Spain ARTICLE INFO Keywords: Silicon carbide SiC MOSFETs Field effect mobility Interface traps Power devices ABSTRACT This paper reviews advanced gate dielectric processes for SiC MOSFETs. The poor quality of the SiO 2 /SiC in- terface severely limits the value of the channel field-effect mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation methods are effective in increasing the channel mobility and have been adopted by manufacturers for the first generations of commercial power de- vices. Gate oxide doping techniques have also been successfully implemented to further increase the channel mobility, although device stability is compromised. The use of high-k dielectrics is also analyzed, together with the impact of different crystal orientations on the channel mobility. Finally, the performance of SiC MOSFETs in harsh environments is also reviewed with special emphasis on high temperature operation. 1. Introduction It is today widely recognized that new generations of power devices based on Wide Band Gap (WBG) semiconductor materials with superior material properties for power operation are required for a higher effi- ciency of power converters, as profusely covered in this special issue. Their critical field is more than one order of magnitude higher than Si, which allows using a thinner and higher conductive epitaxial layer. Consequently, the on-state current losses are drastically reduced. Within the WBG family, SiC is one of the most promising semiconductor materials for power devices fabrication, and indeed several commercial devices are already offered on high volume production. Specifically, MOSFET device is a key element in modern micro- electronics, with applications spanning from highly integrated CMOS to high power devices. As a device, it has really boosted the development of all kind of microelectronic technologies since the 1970's. In power electronics, a technology initially based on Si bipolar devices (BJTs and thyristors), MOSFETs and MOS gate-controlled devices (mainly IGBTs), completely monopolize today's market. Therefore, it seemed logical to endeavor a new generation of SiC power devices based on the devel- opment of MOSFET architecture. Indeed, since its demonstration in 1993 [1], SiC MOSFET has been the focus of numerous investigations. However, the development of low resistance SiC power MOSFETs has been slower than other SiC power switches, like JFETs or BJTs, due to its very low inversion channel mobility values and threshold voltage (V th ) high instability. These limitations are mainly caused by a poor quality of the MOS interface, which is affected by large oxide charges and interface trap density (D it ) values. However, improvements in the MOS interface quality allowed the realization of commercial SiC MOSFETs operative up to 1.2 kV–1.7 kV, yet, SiC high voltage cap- ability is not fully exploited. The current roadmap for SiC semi- conductor industry tentatively predicts the introduction of 3.3 kV–6.5 kV SiC devices in the market in the medium term to compete with their Si-based counterparts. This review compiles several technological solutions focused to improve the SiC MOS interface toward a main target, to increase the channel carrier mobility. Indeed, regarding mobility in the MOSFET channel, we have to consider two ranges of operation, one at relatively low electric field, just above the V th (typically 5 V), and a second regime at higher field, for MOS gate voltages of 15–25 V. The latter is espe- cially relevant for power electronics converters as it corresponds to the gate operation voltage of the devices. There are several ways to extract the channel mobility, coming from Si technology: a) effective channel mobility (μ eff ) is extracted from output curves (dI DS /dV DS ), b) field ef- fect mobility (μ fe ) is extracted from transfer curves (dI DS /dV GS ) and c) hall mobility (μ hall ) is extracted under magnetic field using Hall laws. However, in SiC, the electrons generated in the inversion layer are trapped by the high density of interface traps and near interface oxide charges, and it strongly affects the extraction of an accurate mobility value [2]. Accordingly, the concept of apparent channel mobility would better reflect the mobility extracted from the measurements. In the literature, most of the reported mobility values for SiC MOSFET test structures are specifically field effect mobilities. Experimentally, the μ fe versus gate voltage (or electric field) curve typically shows a peak http://dx.doi.org/10.1016/j.mssp.2017.10.030 Received 1 August 2017; Received in revised form 18 October 2017; Accepted 20 October 2017 ⁎ Correspondence to: CNM-CSIC, C/ dels Tillers, Campus UAB, 08193 Cerdanyola del Valles, Barcelona, Spain. E-mail address: maria.cabello@imb-cnm.csic.es (M. Cabello). Materials Science in Semiconductor Processing xxx (xxxx) xxx–xxx 1369-8001/ © 2017 Published by Elsevier Ltd. Please cite this article as: Cabello, M., Materials Science in Semiconductor Processing (2017), http://dx.doi.org/10.1016/j.mssp.2017.10.030