978-1-5386-9262-2/18/$31.00 ©2018 IEEE Low Power and Energy Efficient Single Error Correction Code using CDM logic style for IoT devices Satwik Gali #1 , Eric Wauer #2 , Tooraj Nikoubin #3 # Texas Tech University, Texas, USA 1 satwik.gali@ttu.edu, 2 Eric.wauer@ttu.edu, 3 tooraj.nikoubin@ttu.edu Abstract— For decades, Error Correction Codes (ECC) have been extensively used to protect the data in registers and memory from errors. The most used ECC’s are Single Error Correction (SEC) codes, which can correct a one-bit error for each word. Due to the recent scale-down in the size of technology, the demand for low power, high speed, and area & energy efficient SEC encoders and decoders have become prominent. Many applications, like IoT devices, memory storage and security applications employing SECs, need reliable hardware at low cost and low power consumption. Significant research has been going on to design efficient ECC’s for energy efficiency and cost optimization. In this paper, Cell Design Methodology (CDM) as an efficient logic style is used for optimization of ECC at the transistor level for improving circuit characteristics. A significant improvement has been recorded by comparing the performance of the SEC codes in terms of power and energy between conventional CMOS (C-CMOS) and CDM logic structures. C-CMOS and CDM standard cells of 10nm, 14nm, 16nm, and 20nm technologies are used to compare the circuit characteristics of the SEC encoder and decoder. The traditional Hamming code and Pedro’s SEC [1] have been used for effective comparison and performance analysis of the cell libraries. This analysis has shown an average improvement of 32.4% on power consumption and 30% on energy consumption by using CDM logic style over the C-CMOS structure. Index Terms—SEC, Hamming code, Energy efficient, Low power SEC, ECC, CDM logic, C-CMOS logic, SEC DED, IoT, Memory storage. I. INTRODUCTION In digital communication, data can be corrupted during the transmission process due to the low-threshold voltage of transistors. Such errors are called soft errors and they should be corrected before the data can be used. To correct these single-bit soft errors, different ECC’s have been designed and implemented over the past few decades. These SEC codes consist of an encoder and a decoder. The hardware of these encoders and decoders are concerned with the number of logic gates, power consumption, and propagation delay and energy efficiency. While writing the data into the memory, the encoder encodes the data and then the decoder decodes it when reading from the memory. This additional circuitry impacts the SEC by reducing the error but affects other performance parameters like power, delay, and energy. There are different models of SEC codes which are more efficient than the conventional Hamming code. The Pedro’s SEC code [1], which exhibited more efficiency than Hamming had been used to compare both models using the C-CMOS and CDM logic structures [2]. This paper focuses on showing the prominence of the realization of the CDM structures in IoT and other memory- related applications [4] by showing the performance comparison of two different SEC codes in both C-CMOS and CDM structures using 10nm, 14nm, 16nm, and 20nm standard cell libraries [2]. The Verilog models of the Hamming and Pedro’s code are used to evaluate the power, delay and energy using the above-mentioned C-CMOS and CDM standard cell libraries in Design Compiler. The remainder of the paper is organized as follows: Section II briefly explains SEC codes and their inner- workings. It explains the process of the encoder and decoder circuits along with the process of bit protection and error correction. Section III explains the CDM logic structure and its importance in the performance- enhancement and transistor-level optimization of hardware. Section IV contains a simulation analysis of the circuit characteristics of the Hamming and Pedro’s code with both C-CMOS and CDM structures using 10nm, 14nm, 16nm, and 20nm standard cell libraries [2]. Section V is the conclusion. II. BACKGROUND A. Error Correcting Code - ECC ECC is a mathematical technique that transforms message data stored in memory into codewords using a hardware encoder to add redundancy for added protection against faults [4]. Many memory storage devices, IoT devices, and data transmission devices rely on ECCs for increased protection against soft errors. These ECCs are specifically desired for high fault-tolerant applications like servers, EDAC memory protection, and deep-space applications. B. Hamming Code The most widely used ECC is Hamming code. In 1950, Richard Hamming introduced the Hamming code. It encodes 8 data bits into 12 bits by appending 4 parity bits [1]. It can detect and correct single bit errors. By appending a parity bit, it can detect two-bit errors but cannot correct Authorized licensed use limited to: Texas Tech University. Downloaded on June 13,2022 at 21:38:28 UTC from IEEE Xplore. Restrictions apply.