This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits Georgios Zervakis , Fotios Ntouskas , Sotirios Xydis, Dimitrios Soudris, and Kiamal Pekmestzi Abstract—Approximate computing emerges as a new design paradigm for generating energy-efficient computing systems. Voltage overscal- ing (VOS) forms a very promising technique to generate approximate circuits, and its application in cooperation to other approximate tech- niques is proven to lead to more efficient solutions. However, the existing design tools fail to provide effective voltage-aware simulation for early exploration of power-error approximate design tradeoffs. In this brief, we propose VOSsim, a framework that extends state-of-the-art industry strength tools, to enable fast and accurate simulations of voltage over- scaled circuits. We extensively evaluate VOSsim showing that it attains 99.2% output and 98.4% power accuracy, with an average speedup of 32× in simulation time compared to high-precision SPICE simulations, i.e., the only available solution today for VOS-aware simulation. Index Terms— Approximate computing, hardware circuits, tim- ing analysis, voltage overscaling (VOS), VOS-aware simulation. I. I NTRODUCTION S INCE the failure of Dennard scaling [1], power consumption has become a first class concern in integrated circuits design. Recently, approximate computing has emerged as a design alternative for energy-efficient system design, trading accuracy for significant energy gains [2]. Exploiting the intrinsic error resilience of a large number of application domains [3], approximate computing aggres- sively decreases power consumption by relaxing the computations’ numerical correctness. In hardware design, approximate computing is applied in three distinct layers [4]–[6], i.e., the algorithmic, e.g., omit computa- tions [5], the logic, e.g., truth table altering [7], and the circuit, e.g., voltage overscaling (VOS) [8]. VOS is applied to any circuit by keeping the operating frequency constant and decreasing the supply voltage below its nominal value [4]. The voltage decrease reduces the power consumption significantly, but erroneous outputs are generated due to the circuit paths that fail to meet the time requirements [8]. Driven by the potential of approximate computing for energy reduction, high interest is shown in the design of hardware approxi- mate accelerators [4]–[6], [9]–[12]. Recent works [2], [4], [6] indicate the benefits originated by the synergistic incorporation of multiple approximate techniques to construct the final accelerator circuit. Notably, it is demonstrated that applying VOS in cooperation to other approximate techniques leads to more efficient solutions. Approx- imate techniques from the logic and algorithmic layers produce simpler circuits and can reduce the circuit’s delay and decrease the number of critical paths [5]–[7]. Hence, applying VOS can further reduce the power consumption, at the cost of a small error increase, as fewer paths are affected by the voltage decrease [9]. Manuscript received October 9, 2017; revised December 28, 2017; accepted January 26, 2018. This work was supported by the European Com- mission under the FP7-612069-HARPA project. (Corresponding author: Georgios Zervakis.) The authors are with the Department of Electrical and Computer Engineer- ing, National Technical University of Athens, 15780 Athens, Greece (e-mail: zervakis@microlab.ntua.gr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2018.2803202 To maximally exploit VOS capabilities, i.e., achieve the highest power reduction for a given error constraint, the power-error tradeoff has to be computed for every circuit architecture and voltage assignment. Typically, time-consuming SPICE simulations are performed to compute the circuits’ power consumption and output errors when applying VOS [8], [9], [13]. To have a good estimation of a circuit’s error statistics when applying VOS, large input data sets have to be used trying to cover all the possible input combinations and transitions (errors due to VOS depend on both the current and the previous inputs) [14]. However, the increased time needed to perform SPICE simulations and the vast size of the input data sets make VOS simulation to quickly become a bottleneck in approximate design flows, especially at the design phase where several architectures with varying configurations are explored. Moreover, the required designer effort to perform SPICE simulations increases as the system complexity scales up [15]. Jeon et al. [15] and Lui et al. [17] perform statistical analysis and apply probabilistic models to calculate computation errors due to VOS, obtaining moderate accuracy results. However, they do not provide a power estimation and cannot directly extend existing hardware design flows. Furthermore, these models fail to capture errors originated by other approximation techniques and thus cannot be used in multilevel approximation. In the approximate comput- ing community, it is more than evident that there is a lack of a VOS specific methodology that rapidly quantifies VOS errors and power savings, thus limiting the potential benefits of stand- alone VOS as well as its cooperation with other approximation techniques [10]–[12]. In this brief, we propose VOSsim, a framework that seamlessly extends typical hardware design flows, enabling for the first time, very fast (an order of magnitude) and accurate voltage-aware circuit simulation at gate level. VOSsim operates over widely used industry strength tools and performs voltage dependent gate level timing sim- ulations to produce the circuit’s output and power consumption at the desired voltage value. Extensive experimental evaluation compared to high-precision SPICE simulations showed that for 1%–20% voltage decrease, the proposed VOSsim framework achieves 99.2% output and 98.4% power accuracy on average, while achieving an average speedup of 32× in simulation time. II. LIMITED VOS SUPPORT IN RTL DESIGN FLOWS In this section, we identify and discuss the limitations of the existing state-of-art hardware design tools that inherently limit non- SPICE VOS simulations. The existing circuit synthesis tools, e.g., Synopsys Design Com- piler and Cadence Encounter register-transfer level (RTL) compiler, given the hardware description of a circuit and the design con- straints (e.g., frequency and voltage value), synthesize the circuit and produce its gate-level netlist based on a provided technology library. However, altering the voltage supply before synthesizing the circuit can lead to different synthesis implementation, and as a result, the voltage decrease must be applied after the synthesized netlist of the circuit is produced. 1063-8210 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.