Thermal Aware FPRM based AND-XOR Network Synthesis of Logic Circuits Apangshu Das ECE Department NIT Agartala Agartala, India apangshuextc@gmail.com Sambhu Nath Pradhan ECE Department NIT Agartala Agartala, India sambhu.pradhan@gmail.com Abstract— With the advent of incorporating increased number of complex logic blocks within a VLSI chip, power-density is increasing. Power-density directly converges into temperature which reduces the yield of the circuit. Adverse affect of power- density reduction is increase in area. So, there is a trade-off between area and power-density. Previous works has been done on the Fixed Polarity Reed-Muller (FPRM) AND-XOR realization for its reduced area or low power realization. In this paper, we present a Genetic Algorithm(GA) based non- exhaustive heuristic to increase the sharing of product terms by selecting the proper polarity of input variables in FPRM expansion and a suitable area and power-density trade-off has been enumerated. Incorporation of the power-density as a fitness constraint in FPRM based optimization for temperature analysis is the first ever effort. The proposed algorithm has been validated with the LGSynth93 benchmark circuit Keywords— FPRM; AND-XOR network; power-density; genetic algorithm; area power-density trade-offs. I. INTRODUCTION Unexpected scaling along with the expeditious enhancement in the functional complexity and miniaturization of the Integrated Circuits (ICs) makes the temperature more significant problem in VLSI design and synthesis methodologies. Solving the crisis of the portability issue arises due to feature size scaling which tremendously increases the total power deployment of the ICs. Consequently, the power-density becomes extensive and generates a thermal effect, which reduces the performance and efficiency of the circuit or can be burnt out due to thermal runaway. In recent time power-density is an important constrain for designing the VLSI circuits with reduced thermal effect, because power-density directly converges to temperature [1]. So, optimizing a circuit taking power-density as a cost parameter is very much important to limit the temperature generation. Temperature got importance by researchers in physical design domain, but the cooling arrangement becomes costly. The cooling arrangement expenditures are rising exponentially at the rate of $ 1-3 or more per watt of power dissipation for high performance CPUs [2, 3]. To reduce the cooling expenditures, design-time thermal aware techniques can be developed to mitigate the effect of power and thermal characteristics of ICs. Logic minimization plays an important role in combinational synthesis domain to optimize the circuit by increasing the shared logic within the functions. The dynamic power consumption can be evaluated by the estimation of switching activity and transition probability from the optimized circuit. Then the power-density is obtained by taking the ratio of the power consumption and the utilized chip area. Here in this paper we have projected a logic synthesizer which tries to optimize the IC area and power-density by enumerating trade-offs between the two and tries to reduce the thermal effect of the combinational logic circuits. Multi-output functions aspire at sinking the circuit area by reaping common terms within the subfunctions. The well-accepted logic synthesizers which had utilized the above logic are Espresso [4] and SIS [5]. Espresso is widely used for two-level AND-OR based PLA structure optimizer with respect to minimized product terms. On the other hand, SIS utilizes multi-level logic circuits to increase the sharing between subfunctions. Most of the AND-OR based logic minimizers are reported in papers [4, 5, 6]. However, in numerous practical circuits used in the fields of coding theory, telecommunication, linear and digital systems, computer arithmetic processing logic units, error correction and detection circuits, data encryption and decryption circuits inherit the basic functions of mod-2 sum form. In such logic circuits, AND-XOR minimized algorithms repeatedly produce more compressed circuit than the PLA based AND-OR realizations. High testability is another important characteristic offered by AND-XOR realized circuits. However, obstacles reduce the popularity of AND- XOR based circuit realization in the application vicinity. i) As compare to the OR gate, XOR gate realization consumes more silicon region along with comparable low speed. ii) More proficiency is required to realize a circuit in terms of AND-XOR functions. The first hindrance has been solved by the new technologies developed on the onset of various field programmable gate array (FPGA) devices, and application specific integrated circuit (ASIC). Recent programmable packages include the XOR gate as universal module. To solve the second problem, optimization techniques has been successfully 497 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS) 978-1-4799-8349-0/15/$31.00 ©2015 IEEE