Sandwiched-Gate Inverter: Novel Device Structure for Future Logic Gates Myunghwan Ryu a , Franklin Bien a , and Youngmin Kim b a School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST), Ulsan, Republic of Korea, b School of Computer Engineering, Kwangwoon University, Seoul, Republic of Korea, youngmin@kw.ac.kr Abstract—In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed. Keywords—component; formatting; style; styling; insert (key words) I. INTRODUCTION Over the last few decades, the size of the transistor has been reduced in order to improve its performance and to integrate more functions into a chip expedited by Moore’s law. With the advancement of manufacturing technology, the transistor has been successfully scaled down to a technology node of 22-nm. However, the ability for gate to effectively control the channel diminishes due to such an aggressive reduction in size. The reduced controllability on the channel results in a significant increase in the leakage current and short channel effects (SCE). Short-channel effects such as subthreshold swing degradation, source/drain leakage current problems, larger drain-induced barrier lowering (DIBL), Vth roll-off, and Vth mismatch caused by random dopant fluctuations lead to dramatic change in the use of conventional planar devices for IC designs [1]. Therefore, the concept of multi-gate, such as double-gate or FinFET and triple-gate transistors, has been proposed and heavily investigated to overcome the bottlenecks for the continuous scaling [2]. As one of the most promising architectures for the ultimately scaled device, the gate-all-around (GAA) silicon nanowire transistor (SNWT) began to attract attention due to its excellent electrostatic capability of the channel control and efficiency of its practical design [3]. The paper is organized as follows: section II describes the proposed novel sandwiched-gate inverter. The proposed inverter can reduce circuit foot print and works properly. Section III describes the verification of the operation of proposed inverter, and Section IV concludes our works. II. PROPOSED NOVEL SANDWICHED-GATE INVERTER In this study, we introduce a novel inverter structure in which the P-type GAA encloses a usual N-type GAA. Our research focuses on the proposal of novel inverter and verification. A sandwiched-gate inverter forms this structure as shown in Fig. 1 (a). A cross-section through the channel region between point A and point A’ is illustrated in Fig. 1(b). As shown in Fig. 1(a) and (b), the NMOS silicon body is in the (a) (b) Fig. 1. Illustration of the proposed sandwiched-gate inverter. (a) 3D cross section, (b) cross section but through the channel region between point A and point A’. SISPAD 2015, September 9-11, 2015, Washington, DC, USA SISPAD 2015 - http://www.sispad.org 442 978-1-4673-7860-4/15/$31.00 ©2015 IEEE