0741-3106 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2016.2632182, IEEE Electron Device Letters > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract— Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device which is based on the silicon-oxide-nitride-oxide-silicon (SONOS) configuration is characterized in two different operational modes, an inversion-mode (IM) and a junctionless-mode (JM). The LF noise showed 1/f–shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability. Index Terms—Gate-all-around (GAA), inversion-mode (IM), junctionless-mode (JM), low-frequency (LF) noise, one-route all-dry etch, SONOS, vertically stacked nanowire (VS-NW). I. INTRODUCTION To suppress the short-channel effects (SCEs) originating from the miniaturization of a MOSFET, structural optimization efforts led to the creation of gate-all-around (GAA) silicon nanowire (Si-NW), which is considered as the ultimate structure to accommodate further aggressive scaling given its outstanding gate controllability [1]–[3]. Another strategy to explore a new device, termed a junctionless-mode (JM) MOSFET [4], sought to move beyond conventional and traditional inversion-mode (IM) MOSFET. Irrespective of the operational mode, an extremely scaled Si-NW structure sacrifices the on-state current (ION), thereby limiting the range This work was sponsored in part by the Pioneer Research Center Program through the National Research Foundation of Korea within the Ministry of Science, ICT & Future Planning under Grant number 2012-0009600 and the Center for Integrated Smart Sensors within the MSIP through the Global Frontier Project under Grant number CISS-2011-0031848. It was also partially supported by Samsung Electronics Co., Ltd. and in part by IDEC (EDA Tool, MPW). T. Bang, B.-H. Lee, C.-K. Kim, D.-C. Ahn, S.-B. Jeon, and Y.-K. Choi are with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, South Korea (e-mail: ykchoi@ee.kaist.ac.kr). M.-H. Kang, and J.-S. Oh are with the National Nanofab Center, Department of Nano-Process, Daejeon 34141, South Korea † These authors contributed equally to this work of applications which use those structures. In particular, the GAA Si-NW transistor for NAND flash memory, where many cells are connected onto a single string, may not be suitable for an array configuration owing to concerns over readout failures stemming from the limited ION [5]. In this regard, a vertically stacked Si-NW (VS-NW) FET can resolve this issue for the NAND architecture due to its high ION and good scalability for high-density operations [6]–[9]. However, the degree of process complexity when creating VS-NW can lead to unwanted damage to the silicon surface and gate dielectric [10], [11] while also affecting the variability. With regard to this type of damage on the silicon surface and gate dielectric, the low-frequency (LF) noise can be characterized [12]–[14]. This letter is focused on the LF noise behavior of five-story SONOS memory. It contains comparative analyses of device performance variations, the effective oxide trap density levels (Nt), and tunneling oxide degradation in the following device structures: five-story IM, one-story JM, and five-story JM SONOS. (The LF noise analysis on the one-story JM were reported in our previous work [15].) II. DEVICE STRUCTURE AND MEASUREMENT For scalability without sacrificing the ION, five-story VS-NW FETs operated by IM and JM were fabricated on a bulk-Si wafer as an experimental group. In addition, one-story VS-NW FETs were fabricated as a control group. All of the structures utilized the GAA configuration and the oxide-nitride-oxide (ONO) configuration as the gate dielectrics. To fabricate the vertically stacked and isolated five-story Si-NWs, the Bosch Low-Frequency Noise Characteristics in SONOS Flash Memory with Vertically Stacked Nanowire FETs Tewook Bang † , Byung-Hyun Lee † , Choong-Ki Kim, Dae-Chul Ahn, Seung-Bae Jeon, Min-Ho Kang, Jae-Sub Oh, and Yang-Kyu Choi S D G Source Drain 500 nm Si substrate Si (a) (b) (c) C4F8 SF 6 SF 6 Fig. 1. (a) Schematic of the fabricated five-story VS-NW FETs with ONO gate dielectrics, (b) schematic of the one-route all-dry etch process (ORADEP) and (c) SEM image of the VS-NW structure formed by the ORADEP [8].