A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry Farhana Begum 1 • Sandeep Mishra 2 • Md. Najrul Islam 1 • Anup Dandapat 1 Received: 12 November 2018 / Revised: 4 February 2019 / Accepted: 2 April 2019 Ó Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of 0:0139 mm 2 . The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V. Keywords Analog-to-digital converter (ADC)  SAR-ADC  Capacitive digital-to-analog converter (DAC)  Control logic  Dynamic comparator  Kick-back noise  Regeneration time 1 Introduction Recent advances in communication systems require larger bandwidth and higher sampling rate of analog-to-digital converter (ADC) [1, 2]. High resolution ADCs are expensive in terms of design space requirement and power dissipation that increases with sampling frequency [3]. With these requirements, thermal noise falls in the spectrum of opera- tion and inevitably affects the signal parameters like signal- to-noise ratio (SNR) and its related parameters. These effects are getting worse in wireless communication device where ADCs act as an integral part of its functionality [4]. The parallel flash ADCs function at high speed but are expensive and have issue of sparkle codes [5, 6]. Sigma- delta (RD) ADCs do not suffer from such noises via the filtering and convert at low power dissipation [7]. However, the operational transconductance as well as the integrators of (RD) architecture of ADCs also affect the operation speed and obstructs in achieving optimum operating frequency. Pipelined ADC make high perfor- mance a challenging task inducing the effects of drain- induced barrier lowering in short channel devices [5]. A solution to these is a successive-approximation-register (SAR) ADC that requires lesser area and therefore is suitable for high resolution designs but the speed of con- version is very less [8, 9]. Analog to digital conversion for SAR-ADCs as in Fig. 1 is performed in several cycles which limits their speed of operation and thereby have achieved tens of MS/s to low GS/s sampling rates [10]. In addition, SAR-ADC and multi-bit SAR-ADC with sam- pling capacitance large enough to achieve suitable SNR leads to lower speed of operation [11–13]. The economical SAR-ADC is the designers’ choice over the years. But, the requirement of high precision with acceptable conversion rate has remained as a challenging task. Key limitations and feasible solutions through design improvements in the SAR-ADC sub-blocks are described as: 1. The conversion in SAR-ADC takes more time of around 1/2 least significant bit (LSB) with large & Anup Dandapat anup.dandapat@gmail.com 1 National Institute of Technology Meghalaya, Shillong, Meghalaya, India 2 Indian Institute of Information Technology Pune, Sudumbare, Maharashtra, India 123 Analog Integrated Circuits and Signal Processing https://doi.org/10.1007/s10470-019-01450-w