S.I. : VISVESVARAYA A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication Farhana Begum 1 • Anup Dandapat 1 Received: 15 January 2018 / Accepted: 7 May 2018 Ó CSI Publications 2018 Abstract The growing need for power aware and energy efficient analog-to-digital converters (ADCs) has led to the development of optimized ADC designs. Though several ADCs are designed using isolated platforms, the usage of hybrid combination has noticeably made an impact in achieving this scenario. The proposed work herein is based on a subranging flash and successive-approximation-reg- ister ADC design. The isolated architectures have been redesigned and it is seen to be efficient with a power reduction by 40%. The utilization of comparator with a proposed charge sharing circuitry produces a lower input referred offset voltage during the comparison stages by eliminating the need of a extra circuitry. However, this increases the kick-back noise accounting for the sure trade- off. To reduce these effects a sample and hold switch is used at the comparator input voltage during the decision mode to minimize the kick-back noise thereby keeping the non-linearity errors at minimal. Energy efficiency of 64% have been seen compared to the referred design due to the proposed charge sharing circuitry during the evaluation phase. The converter achieves 61-dB SFDR and 46.5-dB SNDR at 2.5 GS/s for input signal frequency of 100 MHz with a power dissipation of 10.5 mW at 1 V supply. Keywords Analog-to-digital converter Á Dynamic comparator Á Subranging flash ADC Á Kick-back noise Á Regeneration time Á SAR ADC 1 Introduction There is a tremendous growth from narrow band to wide- band wireless communication owing to its huge interest in several battery operated devices ranging from WIFI, WiMAX to WCDMA and other wireless cellular commu- nications. Analog-to-digital converter (ADC) is an indis- pensable element of such devices and power consumption which is a prime concern in ADCs is mainly due to the presence of comparators and digital-to-analog converters (DACs). Therefore, numerous attempts have been made which includes the majority voting comparison [1] and dual comparator [2] to reduce the power substantially. Various stand alone ADCs namely flash ADCs, successive- approximation-register (SAR) ADCs, sigma delta and dual slope ADCs have been used predominantly. Flash ADCs [3] support very high-speed in a sampling rate of 1–3 GS/s with a medium resolution (6–8 bits) meeting many specific targets. The absence of DAC in a flash structure reduces the energy consumption for high resolutions though often require extensive comparator offset calibration [4] which increases twice exponentially with the number of bits. In contrast, SAR ADCs require very low area and as such are suitable for high resolution–power efficient design but the conversion speed is very less [5]. The integrators and operational transconductance present in delta-sigma ADCs affect the speed of operation and hinders in attaining sustainable operating frequency. However, this can be improved manifold using an optimized integrator by con- necting it to the ends of a capacitor. Scaling and opti- mization of these designs also poses as a challenging task. Subsequently, dual-slope ADCs and single slope ADCs have been found to be improved by connecting the inte- grators to capacitive circuits. With binary search bootstrap between the comparator efficiency is also increased but & Anup Dandapat anup.dandapat@gmail.com 1 National Institute of Technology Meghalaya, Shillong, Meghalaya, India 123 CSIT https://doi.org/10.1007/s40012-018-0190-3