International Journal of Electrical and Computer Engineering (IJECE) Vol. 12, No. 6, December 2022, pp. 5840~5847 ISSN: 2088-8708, DOI: 10.11591/ijece.v12i6.pp5840-5847  5840 Journal homepage: http://ijece.iaescore.com Range-enhanced packet classification to improve computational performance on field programmable gate array Anita Ponnuswamy, Manju Devi Department of Electronics and Communication Engineering, The Oxford College of Engineering, Visvesvaraya Technological University, Bangalore, India Article Info ABSTRACT Article history: Received May 15, 2021 Revised May 31, 2022 Accepted Jun 29, 2022 Multi-filed packet classification is a powerful classification engine that classifies input packets into different fields based on predefined rules. As the demand for the internet increases, efficient network routers can support many network features like quality of services (QoS), firewalls, security, multimedia communications, and virtual private networks. However, the traditional packet classification methods do not fulfill today’s network functionality and requirements efficiently. In this article, an efficient range enhanced packet classification (REPC) module is designed using a range bit-vector encoding method, which provides a unique design to store the precomputed values in memory. In addition, the REPC supports range to prefix features to match the packets to the corresponding header fields. The synthesis and implementation results of REPC are analyzed and tabulated in detail. The REPC module utilizes 3% slices on Artix-7 field programmable gate array (FPGA), works at 99.87 Gbps throughput with a latency of 3 clock cycles. The proposed REPC is compared with existing packet classification approaches with better hardware constraints improvements. Keywords: Field programmable gate array Header fields Matching operations Packet classification Range bit-vector encoding Prefix range Range enhanced Ruleset This is an open access article under the CC BY-SA license. Corresponding Author: Anita Ponnuswamy Department of Electronics and Communication Engineering, The Oxford College of Engineering, Visvesvaraya Technological University Bangalore, India Email: anita.p.research@gmail.com 1. INTRODUCTION The network routers provide many features like quality of services (QoS), scheduling, access control, and security. These features in network routers can differentiate between different packets and decompose or classify them into the flow. The collection of packets has the same header features with different payloads known as flow mechanisms. Network routers provide packets with a proper flow mechanism that agrees on the set of predefined rules. The classifier collects these rules, and each rule in the packet classifier defines the flow of the packet, and it belongs to which field [1]. The packet classifier has met metrics like fats updating, fields used, memory requirements, flexibility, and search speed to improve network computational performance. In general, packet classification approaches are classified based on multiple field search techniques like Tuple space, decision-tree (DT) based, decomposition, and exhaustive search. The tuple space approach includes rectangle search, pruned tuple search, and tuple search algorithms. Similarly, the decision tree classification approach includes a grid of tries, Hypercuts, HiCuts, and modular packet classification algorithms. The decomposition approach includes cross producing, parallel bit-vector, aggregated bit-vector, and recursive-flow classification (RFC). Finally, the exhaustive search contains ternary content addressable memory (TCAM), emulated TCAM, linear search, and bit map insertion approaches [1]–[3].