IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 25, NO. 21, NOVEMBER 1, 2013 2133 Multiplier-Free Joint Carrier Recovery for 16-QAM Synchronous or Agile Burst Receivers Igor Tselniker, Alex Tolmachev, and Moshe Nazarathy, Senior Member, IEEE Abstract— Multiplierless multi-symbol delay detector, recently demonstrated in FPGA for QPSK and 16-QAM at 25 Gbaud for phase recovery, is augmented here to also mitigate frequency offset exceeding half the baudrate and chirp <80 GHz/us, also multiplier-free (just simple additions/logic operations)— applicable to synchronous and burst-receivers. Index Terms—Optically coherent detection, phase estimation, phase recovery, multi-symbol delay detection (MSDD), multi- symbol phase estimation (MSPE), carrier frequency offset (CFO), frequency offset estimation. I. I NTRODUCTION T HE literature is replete with a plethora of carrier phase and/or frequency recovery methods for coherent detection (see [1] for a review). One particular method, namely Multi- Symbol Delay Detection (MSDD) aka Multi-Symbol Phase Estimation (MSPE) has been fruitfully pursued [1]–[6] but is yet to receive mainstream recognition in the carrier recovery (CR) area despite superior performance. MSDD is a decision- directed (DD) CR, yet differing from a DD PLL. MSDD operation is cycle-slips free, as it is used in conjunction with modulus-preserving differential precoding (DP) [4], [6] at the QAM Transmitter (Tx). Typically DP incurs an OSNR penalty, however in the case of MSDD, the DP penalty may be made negligible at least in white noise (as was shown years ago in the wireless literature [7] but not yet assim- ilated by our optical communication community). Recently, we have demonstrated [5] a QPSK / 16-QAM polar-domain MSDD variant realized without any multipliers and amenable to “superscalar” HW parallelization, without compromising its phase recovery performance. We constructed FPGA HW prototypes at 25 Gbaud [5], [9] which to our knowledge are the fastest QPSK and 16-QAM CRs to have ever been made to work in electrical real-time. Those HW demonstrations attested to the very low computational burden in the polar MSDD structure. Moreover, in comparison with our prior non-polar MSDD CR versions [4], the new polar MSDD exhibits negligible performance penalty, in exchange for the Manuscript received June 13, 2013; revised August 23, 2013; accepted September 11, 2013. Date of publication September 18, 2013; date of current version October 9, 2013. This work was supported in part by the the Chief Scientist Office of the Israeli Ministry of Industry, in part by the Trade and Labor - “Tera Santa” consortium under the Magnet program as well as the Israel Science Foundation, and in part by the ASTRON FP7 European project. The authors are with the Technion, Israel Institute of Technology, Haifa 32000, Israel (e-mail: igortz@tx.technion.ac.il; talex@tx.technion.ac.il; nazarat@ee.technion.ac.il). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LPT.2013.2282311 multiplier-less realization major benefit. In this letter the polar- MSDD phase-recovery system [5] is augmented by a novel agile carrier frequency offset (CFO) estimation (EST) module comprising just 11 adders. The resulting polar MSDD with joint phase and frequency EST is applicable to synchronous coherent receivers (Rx), wherein low-complexity and high performance are at a premium. Moreover, the new CR is highly suitable for agile wideband coherent burst receivers [9]–[11] emerging in metro networks, wherein the optical packet bursts must be rapidly acquired by coherent LO tuning with large CFO laser transients [12]. II. OVERVIEW OF PROPOSED CR CHARACTERISTICS The new extra capability of CFO mitigation is obtained (Fig. 1) by appending here the module marked “CFO EST” atop the polar-MSDD [5] which originally provided just phase estimation. Negligible Complexity: The original polar MSDD system, was realized multiplier-less as demoed in FPGA [5]; the CFO EST mitigation upgrade module is also implemented with no multipliers, requiring just 11 adders total, some delays and trivial bit-shift scalings by powers-of-two. CFO capture range: The peak-to-peak CFO range captured by our new joint phase and frequency EST exceeds 0.5 R s where R s is the baudrate. The precise value of the CFO capture range (>half-baudrate) is OSNR-dependent, tending to R s in asymptotically large SNR. Negligible OSNR penalty: One should be concerned about potential phase noises leakage through the new CFO EST module. Fortunately, in the new system the incremental degra- dation of the phase recovery tolerance is negligible - just 0.2 dB penalty due to the CFO EST. Advantages for coherent burst receivers: The proposed CR advances the state-of-the-art of coherent burst receivers, wherein robust differential precoding and decoding methods have been recently introduced [11]. For coherent agile burst- receiver applications, it is critical to tolerate large and rapid CFO swings during the burst transients of the LO. In these prior coherent burst receivers, the CFO tolerance was achieved by adopting simple soft differential [4], [6], [13] or doubly differential [12] decoding (as opposed to ‘hard’ or ‘logical’ differential decoding, ahead of the slicer [14]). However each phase soft differencing at least doubles the ASE noise, thus substantial OSNR penalty is incurred in those current approaches. In contrast, in our proposed solution, robust CFO acquisition is not accompanied by a large OSNR penalty; our OSNR penalty due to incorporating the CFO mitigation is just 0.2 dB. 1041-1135 © 2013 IEEE