ASIC Low-Power ECG-Based Processor for Predicting Cardiac disease S. Devi Poonguzhali Assistant Professor in Department of Electronics and Communication Engineering K. Ramakrishnan College of Technology Trichy, India S.Kanimozhi, R.Karthika, R.Kirthiga UG Student,Department of ECE K.Ramakrishnan College of Technology Trichy,India Abstract— This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier.Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm2 area and consumed 2.78-μW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset. Keywords—Component; formatting; style; styling; insert (key words) I. INTRODUCTION Sudden cardiac death accounts for approximately 300000 deaths in the United States per year, and, in most cases, is the final result of ventricular arrhythmias, including ventricular tachycardia (VT) or ventricular fibrillation (VF). Ventricular arrhythmia is an abnormal ECG rhythm and is responsible for 75%–85% of sudden deaths in persons with heart problems unless treated within seconds. Most ventricular arrhythmias are caused by coronary heart disease, hypertension, or cardiomyopathy, and Some components, such as multi-leveled equations, graphics, and tables are not prescribed, although the various table text styles are provided. The formatter will need to create these e if not accurately diagnosed nor treated, immediate occurs death. VT is a fast rhythm of more than three consecutive beats originating from the ventricles at a rate more than 100 beats/min . VF is another rhythm characterized by the chaotic activation of ventricles, and it causes immediate cessation of blood circulation and degenerates further into a pulseless or flat ECG signal indicating no cardiac electrical activity. The implantable cardioverter-defibrillator has been considered as the best protection against sudden death from ventricular arrhythmias in high-risk individuals. However, most sudden deaths occur in individuals who do not have high-risk profiles. Long-term ECG monitoring is the criterion standard for the diagnosis of ventricular arrhythmia. The 12- lead ECGs are obtained and analyzed to detect any changes in the characteristics of the ECG signal.By extractinginformation about intervals, amplitudes, and waveform morphologies of the different P-QRS-T waves, the onset of the ventricular arrhythmia can be detected. A wide range of methods were developed to detect ventricular arrhythmia based on morphological, spectral , or mathematical features extracted from the ECG signal. Machine learning techniques, such as neural networks and support vector machine (SVM) have also been suggested as a useful tool to improve the detection efficiency. Although these methods have exhibited advantages in the detection of ventricular arrhythmia, they have some shortcomings. Some are too difficult to implement or compute, some have low specificity in discriminating between normal and abnormal conditions, and all maintain late detection interval, which is usually not enough to take an action. Recently, due to the remarkable advancement in technology, the development of dedicated hardware for accurate ECG analysis and classification in real time has become possible. The main requirements are low-power consumption and low-energy operation in order to have longer battery lifetime along with the small area for wearability. Many attempts succeeded to implement ECG signal processing and classification systems in Shiuetal.The ESP Block is implementedan integratedelectrocardiogramsignal processor (ESP) for the identification of heart diseases using the 90-nm CMOS technology.The system employedan instrumentationamplifier and a low-pass filter (LPF) to remove the baseline wander and the power line interference form the ECG and employed First, confirm that you have the correct template for your paper size. This template has been tailored for output on the A4 paper size. Another ESP was proposed in the system was fabricated on the 0.18-μm CMOS technology and executed different functions for the three stages of preprocessing, feature extraction, and classification.The algorithm behind these functions was based on the quad level vector . Moreover, the functions were all pipelined to increase hardware utilization and reduce power consumption. Besides, the system employedclock gatingtechniquesto enable anddisable each processing unit individually according to the need and it applied voltage scaling up to 0.7 V. The ECG processor International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Published by, www.ijert.org ICONNECT - 2017 Conference Proceedings Volume 5, Issue 13 Special Issue - 2017