Research Article Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding Latika Desai and Suresh Mali Dr. D. Y. Patil Institute of Technology, Savitribai Phule Pune University, Pune, India Correspondence should be addressed to Latika Desai; latikadesai@gmail.com Received 17 May 2018; Revised 16 August 2018; Accepted 1 September 2018; Published 27 September 2018 Academic Editor: Maurizio Martina Copyright © 2018 Latika Desai and Suresh Mali. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic sofware solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. Tis paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. Te challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state- of-the-art hardware implementations. 1. Introduction In the today’s Internet era, there is a need of protection of Critical Information (CI) like Personal Identifcation Num- ber (PIN) of Automated Teller Machine (ATM) card, One Time Password (OTP), bank transactions, etc. while com- municating CI in open channel system (internet). To avoid unauthorized access, one can encrypt CI itself before it actu- ally gets transferred from one location to another. However, such encrypted CI is still specifcally available to any hacker and will be in a position to extract CI. Terefore, to make highest security of CI, Steganographic data hiding techniques are used to keep the communication of CI itself hidden from the hacker. Many such techniques have been proposed earlier, which comes under two categories, namely, spatial domain and frequency domain. Most of the researchers are focused on the sofware-data hiding through diferent approaches like Least Signifcant Bit (LSB), 2/3 LSB, n-bit LSB, DCT, and Discrete Wavelet Transform (DWT). Unfortunately, sof- ware-data hiding techniques are generic, complex, and slow. Terefore these techniques are not suitable for real-time applications such as ATM where uploading authentication cre- dentials (as CI) through Internet is always essential. Authen- ticating mobile wallets, online Stock trading, and many more real-time e-transactions applications are to be supported by cryptographic and steganographic security systems. Researchers are constantly trying to improve the capa- bilities of reversible Steganographic data hiding methodolo- gies in terms of parameters such as embedding capacity, imperceptibility, security, time complexity, and robustness. Implementation of embedding function (f Em ) and extraction function (f Ex ) may be in either sofware or hardware platform. Hardware implementation has always ofered advantages over sofware realization [1] in terms of low execution time, low power consumption, high reliability, and real- time performance. Implemented hardware can also be made compatible with existing consumer electronics communicat- ing devices. Table 1 also narrates many more advantages of hardware approaches by [1–3]. Hindawi VLSI Design Volume 2018, Article ID 4804729, 8 pages https://doi.org/10.1155/2018/4804729