Studying the inﬂuence of chip temperatures on timing integrity András Timár, Márta Rencz Budapest University of Technology and Economics Department of Electron Devices Budapest, Hungary 1111 Email: timar|rencz@eet.bme.hu Abstract—Thermal (side-)effects can detrimentally inﬂuence operation of integrated circuits. The increase of temperature changes the devices’ characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also brieﬂy presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperature- dependent delays during the running simulation. Index Terms—electro-thermal simulation, temperature distri- bution, timing integrity, delay back-annotation I. I NTRODUCTION In this paper an improved version of CellTherm presented in [1] is reviewed as well as the characterization of cells in the library for temperature-dependent delays. Simulations were run in order to determine how the temperature ﬂuctuations affect the cell delays in a certain standard cell library. The sim- ulated standard cell library was a TSMC 0.35um technology design kit. With the chosen cell library simulations conﬁrmed that with increasing device temperature, cell delays are also increasing. Logic simulations conﬁrmed that the increased delays can mistune setup and hold timing so the circuit may fail to operate correctly. Using the simulation data, exact temperature-delay functions of the standard cells have been acquired. II. RELATED WORK The authors of [2] propose a methodology that constitutes the basic idea of this paper. It deals with temperature map generation of ICs from digital simulations. The method pre- sented in this paper improves that methodology by allowing in-situ logic and thermal co-simulation of an IC design. The work presented in [2] lacks the possibility of back-annotating temperature-dependent delays into the running simulation. Dealing with temperature-dependent delays become more and more important as feature size is shrinking and power density is growing. Failure to take the temperature-dependent delays into account can cause timing (e.g. setup- and hold time) violations that can foil correct logic operation. The methodol- ogy presented in this paper also improves the work of Torki et al by coupling the logic and thermal simulator engines with a custom controller and visualization application that can evaluate logical and thermal calculations and prepare delay back-annotation on-the-ﬂy, in the middle of the simulation. Present electro-thermal simulators approach the electro- thermal simulation problem either by FEM simulation, relax- ation method or simultaneous iteration [3]. A brief overview of an electro-thermal simulation method based on simultaneous iteration is presented in [4] and [5]. A method of electro- thermal simulation using simulator coupling is presented in [6]. The technique is based on the coupling of a FEM program with a circuit simulator. Device level electro-thermal simula- tion of analog circuits and the logical gate level logi-thermal simulation of digital circuits are addressed in [7]. A work of A. Poppe et al. is presented in [8] that gives an overview of different approaches to die level electro-thermal simulation where simulator coupling or the so called direct method (co-simulation of the electrical and thermal parts within a single tool) are used. A pre-RTL temperature-aware design methodology is presented in [9], where a fast, yet accurate architectural thermal model that is able to explore large regions of the design space is proposed. [10] attempts to show that there is a signiﬁcant peak temperature reduction potential in managing lateral heat spreading through ﬂoorplanning. As a demonstration, it uses a wire delay model and ﬂoorplanning algorithm based on simulated annealing to present a proﬁle- driven, thermal-aware ﬂoorplanning scheme that signiﬁcantly reduces peak temperature with minimal performance impact that is quite competitive with Dynamic Thermal Management (DTM). The ﬂoorplanning tool HotFloorplan is part of the HotSpot software [11] that is developed at DCS, University of Virginia. In addition, simulating the self-heating of the circuit in the early phase of the design before manufacture would make cooling issues less problematic. Self-heating simulations may also eliminate the need for design back-annotation after manufacture. An example of temperature-aware ASIC design ﬂow can be found in [12]. Thermal issues in today’s many- and multi-core designs became a primary concern. Multi-core exacerbates thermal challenges because power scales with the number of cores, but also creates new opportunities for temperature-aware design, because multi-core designs offer more design parameters than single-core designs. [13] investigates the relationship between 