International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-9 Issue-1S3, December 2019 101 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number: A10211291S319/2019@BEIESP DOI:10.35940/ijeat.A1021.1291S319 Abstract: Living in this modern era – the epitome of communication GSM networks is one of the mainly used architectures. But GSM architecture has its own shortcomings; the GSM network is vulnerable to various security threats. For any network to provide security to the user, the algorithms should be planned and designed in such a way that it provides cellular secrecy, data and signaling confidentiality to the concerned user. Keeping in mind the above features, the A5/1 algorithm provides network security. Initially, the A5/1 algorithm dealt with a pre-defined secret key but they still possess the threat of being decrypted by cryptanalytic attacks. Although decrypting this algorithm is not easy and requires high computational power. Such attacks lead to the necessity to modify the A5/1 algorithm; in our paper, we have proposed a better method to enhance the already existing algorithm. Keywords: A5/1 algorithm, GSM Networks, non-linear, session key, stream cipher. I. INTRODUCTION The Global System for Mobile Communication (GSM) is extensively used but there is various advanced communication architecture. GSM architecture deals with various network sublevels consisting of the Network and Switching Subsystem (NSS), Base-Station Subsystem (BSS), Mobile Station (MS) and the Operation and Support Subsystem (OSS). The figure below shows the proposed networking system. Fig. 1. GSM Architecture Diagram The existing A5/1 algorithm ensures mobile security by generating a 64-bit secret key which is randomly generated Revised Manuscript Received on December 05, 2019 * Correspondence Author Farhan Rahman*, Electronics and Communication Engineering, Vellore Institute of Technology, Chennai, India . Email: farhanrahman02@gmail.com Siddharth Singh, Electronics and Communication Engineering, Vellore Institute of Technology, Chennai, India . Email: sidssr2012@gmail.com and with the repeated XOR-ing operation of the tapped bits of the Linear Feedback Shift Register (LFSR). The existing A5/1 uses a linear operation like XOR-ing the bit values but our proposed idea uses a non-linear function implemented by MOSFET. The existing A5/1 algorithm has less complexity because of the use of XOR-ing operation with the randomly generated session key. II. RELATED WORK The already existing research and work show that there are various vulnerabilities to the A5/1 Algorithm, such as authentication of a call, maintaining the call, integrity and monitoring the authorization and accessibility. Threats like eavesdropping, impersonation of the user, impersonation of the network, Man-in-the-Middle (MITM), Network authentication compromise possess leakage of user data. The A5/1 algorithm is weak because of the use of linear function; our proposed work increases the complexity by using non-linear function and by increasing the data size of the session key to 128, increasing the size of the LSFR and by altering the tapped bits. In general, the A5/1 algorithm uses a randomly generated 64-bit session with a frame counter. Initially, the register value is set to zero; the ith key gets added to the LSB (least significant bit) and using XOR, for every cycle. Every register is clocked afterward; the same method is used for the 22-bit frame counter. III. EXISTING A5/1 ALGORITHM Following are the steps of the original A5/1 algorithm from the generation of 228-bits of the key sequence [1]: Step 1. All three registers are set to 0. V1 = V2 = V3 = 0 and set the corresponding clocking and tapped bit values set. Step 2. The registers with a size of 64 bits are passed into all registers at the same time. This key is generated during the authentication of a mobile device to the network. Then, the key is consecutively XOR-ed in parallel to the feedback of the registers, for the following next 64 cycles using the algorithm: For i = 0 to 63 do V1[0] = V1[0] ⊕ Jc[i] ,V2[0] = V2[0] ⊕ Jc[i] ,V3[0] = V3[0] ⊕ Jc[i] all the registers are clocked ignoring the stop/go clocking unit. The end for the loop. Step 3. In this step, the clocking of the register takes place 22 times ignoring the irregular clocking. Key bits of a 22bit frame counter of the GSM frame is inserted and XORed with the feedback of each register. Enhancement of A5/1 Stream Cipher with Non-Linear Function using MOSFET Farhan Rahman, Siddharth Singh