Opportunities of CMOS-MEMS integration through LSI foundry and open facility Yoshio Mita 1,2,3 *, Eric Lebrasseur 2 , Yuki Okamoto 1 , Frédéfic Marty 4 , Ryota Setoguchi 1 , Kentaro Yamada 1 , Isao Mori 1 , Satoshi Morishita 1 , Yoshiaki Imai 1 , Kota Hosaka 1 , Atsushi Hirakawa 1 , Shu Inoue 1 , Masanori Kubota 1 , and Matthieu Denoual 3,5 1 Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan 2 VLSI Design and Education Center, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan 3 LIMMS, UMI2820 CNRS France and IIS The University of Tokyo, Meguro, Tokyo 153-8505, Japan 4 ESIEE, University of Paris-Est, 2 bd Blaise Pascal, Noisy-le-Grand 93160, France 5 GREYC, CNRS UMR6072, ENSICAEN, 6 bd Marechal Juin, Caen 14000, France *E-mail: mita@if.t.u-tokyo.ac.jp Received December 13, 2016; accepted February 13, 2017; published online May 19, 2017 Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions. © 2017 The Japan Society of Applied Physics 1. Introduction Since the early days of the micro-electro-mechanical system (MEMS), 1,2) integration with electron devices, which are generally called CMOS-MEMS, has been one of the major axes of research and development. After the successful fabrication demonstration of many devices such as integrated pressure sensors, 3,4) arrayed uncooled bolometers, 5,6) and arrayed micromirror actuator devices, 7) the majority of commercial MEMS devices in the 2015s are combined with integrated circuits. 8) While the MEMS part senses the physical world or acts on the physical world, integrated electronics are useful for signal conditioning (e.g., amplifi- cation, filtering, and analog-to-digital conversion) and communication. IC and MEMS can be combined in the same package [i.e., system-in-package (SiP) 9) ] or on the same chip [i.e., system-on-chip (SoC) 10–13) ]. Industry is putting much effort and money on various approaches to MEMS and IC integration. In pushing forward this integration race, research and=or educational institutions may lag behind because of the required costly facility investments and know-how. On one hand, for research on VLSI, a “sharing economy” system called the “multichip foundry” scheme has been applied since 1981 to overcome the systematic resource disadvantage, as illustrated in Fig. 1(a). In this scheme, LSI designs from independent users share the same LSI fabrication procedure to divide fabrication costs by the number of participants. The pioneering foundries are MOSIS 14) in the United States and CMP 15) in France. In Japan, the VLSI Design and Education Center (VDEC) 16) of the University of Tokyo, established in 1996, has been playing a major role as an active academic foundry center to date. The same idea has been applied to MEMS fabrication such as the MUMPs multiuser project 17) for MEMS (non- CMOS) structures. However, most of the new MEMS devices are still fabricated using a dedicated process in individual cleanroom fabrication sites [Fig. 1(b)]. The major reason that we have identified is the difficulty in process standardization; in research and development stages of a MEMS device, the researchers and engineers want to try to invent new and dedicated fabrication processes as well as new circuit ideas (and eventually protect them with patents), in contrast to the VLSI circuit research in which most of the researchers are satisfied with the fixed fabrication process. The problem is that a multiuser project is successful only when the process is well established and many designers want to use it. Therefore, a multichip project has been proposed mainly for VLSI, and for some particular process sets of MEMS, but for very few CMOS-MEMS integration schemes. This is the fundamental dilemma that has not been clearly solved until recently. On the other hand, since the early 2000s, national network activities to make micro- and nanofabrication facilities open to academic and industrial research and developments have been carried out [Fig. 1(c)]. The three major platforms are the National Nanotechnology Coordinated Infrastructure (NNCI) 18) funded by the National Science Foundation in the United States, the National Technological Research Base (RTB-RENATECH 19) ) funded by the Ministry of Research and Higher Education of France and operated by the French National Research Center (CNRS), and the National Nano- technology Platform 20) funded by the Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT). The idea is to establish large networked national platform centers of micro- and nanofabrication and make them accessible to researchers who do not necessarily have such large and costly facilities. In a platform, researchers can use not only the facilities by themselves but can also ask research engineers of the platform to do process operations in place of them and=or do process operations altogether; the researchers can thereby find the best available way to solve their particular problems, together with technological assis- tance by the platform engineers and researchers. In Japan, 16 institutes are registered as nanofabrication centers, 21) includ- ing the UTokyo VLSI Design and Education Center’s Japanese Journal of Applied Physics 56, 06GA03 (2017) https://doi.org/10.7567/JJAP.56.06GA03 PROGRESS REVIEW 06GA03-1 © 2017 The Japan Society of Applied Physics