0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2870084, IEEE Transactions on Power Electronics IEEE TRANSACTIONS ON POWER ELECTRONICS Design Considerations and Development of an Innovative Gate Driver for Medium Voltage Power Devices with High dv/dt Anup Anurag, Student Member, IEEE, Sayan Acharya, Student Member, IEEE, Yos Prabowo, Student Member, IEEE, Ghanshyam Gohil, Member, IEEE and Subhashish Bhattacharya, Senior Member, IEEE Abstract—Medium Voltage (MV) Silicon Carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5 kV to 10 kV) and a very high dv/dt (10 kV/μs to 100 kV/μs). Using these devices calls for a gate driver with a dc-dc isolation stage which has ultra-low coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. A medium voltage isolation transformer is designed with a low inter-winding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short circuit protection scheme specifically designed for 10 kV SiC MOSFETs. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for medium voltage SiC devices exhibiting very high dv/dt. The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices. Index Terms—Boost converter, buck converter, continuous tests, coupling capacitance, double pulse test, dv/dt immunity, gate driver, medium voltage, silicon carbide devices I. I NTRODUCTION W ITH the advancement of wide bandgap semiconduc- tors, power devices such as silicon carbide metal- oxide-field-effect transistors (SiC-MOSFETs) and silicon car- bide insulated-gate-bipolar transistors (SiC-IGBTs) are now available with blocking voltages upto 15 kV [1]. A 4H-SiC n- IGBT with a blocking voltage up to 27.5 kV is demonstrated in [2]. Applications which require a blocking voltage of 1.2 kV to 10 kV are primarily dominated by SiC MOSFETs Manuscript received April 30, 2018; revised July 22, 2018; accepted September 3, 2018. Recommended for publication by Associate Editor: XXX. This is the preprint version of a paper accepted in IEEE TRANSACTIONS ON POWER ELECTRONICS. Anup Anurag, Sayan Acharya, Yos Prabowo and Subhashish Bhattacharya are with the Department of Electrical and Computer Engineering, North Car- olina State University, Raleigh, NC 27606 USA (email: aanurag2@ncsu.edu, sachary@ncsu.edu, yprabow@ncsu.edu and sbhatta4@ncsu.edu). Ghanshyam Gohil is with the Department of Electrical Engineering, The University of Texas at Dallas, Dallas, TX 75080 (email: ghanshyam.gohil@utdallas.edu). Transformer Driver (H-bridge) Power Isolator (Transformer) Control Signal Isolator (Optic Fiber) Rectifier Diode Array Gate Driver Power Signal Isolation Gap Switch Fig. 1: General schematic of the architecture of a gate driver circuit. The transformer driver provides a high frequency ac signal to the transformer. The power isolation stage can be realized using various methods such as conventional transformers, coreless transformers and power over optics (PoF) etc. The signal isolation is generally done through optcouplers, digital isolators or optical fibers. owing to its small on-state resistance [3]. While gate drivers are commercially available for SiC devices with a blocking voltage range of 650 V - 1700 V, there are a very few commercial gate drivers for 10 kV SiC MOSFETs due to the challenges associated with them [4]. The MV SiC MOSFETs’ fast switching transients can result in a dv/dt as high as 100 kV/μs, which imposes a requirement for a very low isolation capacitance in the gate drive circuit [5], [6]. Also, the severe dv/dt stresses reduces the lifetime of the insulation material over time [7]. Medium voltage gate drivers must provide at least two functions which includes the signal transmission and the power transmission as shown in Fig. 1. The signal transmission can include signals for PWM pulses, protection, monitoring the health of the devices etc. For signal transmission, amongst all the solutions used like optocouplers [8], coreless transformers [9], classical transformers [10] etc, optical fibers seem to be best suited on account of its transmission speed and insulation voltage capability [11]. However, designing the power trans- mission stage still remains as a challenge basically due to three main reasons: • High isolation requirements • Low coupling capacitance • Optimized gate driver footprint It becomes necessary to satisfy all these requirements simul- taneously, and since the requirements counter one another, it becomes imperative to have an optimum trade-off between them, with the isolation requirements and the low coupling capacitance being the highest priority ones. The high dv/dt during the turn-on and turn-off of the SiC MOSFETs is a major concern. The high dv/dt leads to the disruption of the control