The first stage is a second-order modulator using a 1 bit quantiser and the second stage is a second-order modulator using a multibit quantiser. The multibit D/A conversion error -150 -125 -100 -75 -50 input amplitude, dBV Fig. 2 Comparison of SNR against input amplitude RMS nonlinearity of 3 bit D/A convenor is 5% of LSB voltage (i) conventional fourth-order modulator with ideal D/A convertor (ii) new modulator with ideal D/A convertor (iii) conventional fourth-order modulator with nonideal D/A con- vertor (iv) new modulator with nonideal D/A convertor 90 86- 82- 78- 74- 70 -5 -A -3 -2 -1 0 1 2 3 relative gain error ,7. Fig. 3 SNR against error in the integrator gains of the new modulator Input is a 1 kHz sinusoid with magnitude of —40dBV; RMS nonlinearity of 3 bit D/A convertor is 5% of LSB voltage is subject to a second-order noise shaping in the proposed modulator. In a practical implementation, the system per- formance is mainly limited by the mismatch between the SC circuits and digital circuits as in conventional MASH struc- tures. However, the benefit of using the multibit quantiser in the second stage is the reduced total noise power at the system output and thus reduced requirement on the following digital filter. The idea of using a 1 bit quantiser in the first stage and an n-bit quantiser in the following stages can be practiced in general MASH structures. Acknowledgments: This work was financially supported by the Swedish National Board for Industrial and Technical Devel- opment (NUTEK). The valuable discussions with H. Traffand B. Jonsson are highly appreciated. (c) IEE 1993 25th February 1993 N. Tan and S. Eriksson (Dept. of Electrical Engineering, Linkoping University, S-581 83 Linkoping, Sweden) References 1 CANDY, j. c, and TEMES, G. C. (Ed.): 'Oversampling delta-sigma data converters: theory, design and simulation' (IEEE Press, 1992) 2 RITONIEMI, T., KAREMA, T., and TENHUNEN, H.: 'Design of stable high order 1-bit delta-sigma modulators'. Proc. IEEE Int. Symp. Cir- cuits and systems, 1990, pp. 3267-3270 3 FERGUSON, p. F., JUN., GANESAN, A., and ADAMS, R. w.: 'One bit higher order sigma-delta A/D converters'. Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 890-893 RIBNER, D. B. : 'A comparison of modulator networks for high-order oversampled £A analog-to-digital converters', IEEE Trans., Feb- ruary 1991, CAS-38, pp. 145-159 BAHER, H., and AFIFI, E.: 'Novel fourth-order sigma-delta conver- tors', Electron. Lett., July 1992, 28, pp. 1437-1438 LESLIE, T. c, and SINGH, B. : 'Sigma-delta modulators with multi-bit quantising elements and single-bit feedback', IEE Proc. G, June 1992,139, (3), pp. 356-362 HARRIS, F., BROOKING, E., and MCKNIGHT, B.: 'Improved per- formance of multi-bit delta-sigma analog to digital converters via requantisation'. Proc. IEEE Int. Symp. Circuits and Systems, 1991, pp. 1629-1632 LARSON, L. E., CATALTEPE, T., and TEMES, G. c : 'Multi-bit over- sampled SA convertor with digital error correction', Electron. Lett., August 1988, 24, pp. 1051-1052 HAIRAPETIAN, A., TEMES, G. c, and ZHANG, z. x.: 'Multibit sigma- delta modulator with reduced sensitivity to DAC nonlinearity', Electron. Lett., May 1991, 27, pp. 990-991 NOVEL CELL ARCHITECTURE FOR HIGH PERFORMANCE DIGIT-SERIAL COMPUTATION A. Aggoun, A. Ashur and M. K. Ibrahim Indexing terms: Digital arithmetic, Pipeline processing A new cell architecture for high performance digit-serial com- putation is presented. The design of this cell is based on the feedforward of the carry digit, which allows a high level of pipelining to increase the throughput rate. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. The effect of the number of pipelining levels on the throughput rate and hard- ware cost are presented. Introduction: Many structures based on the digit-serial approach have been proposed in the literature [1-4]. Smith et al. [1, 2] have proposed a technique, based on radix-4 and radix-16 computation, to increase the throughput rate of the bit-serial systems. The structure is based on using twin pipe- line and the basic building blocks of the bit-serial systems. The main drawback of this approach is that it was obtained in an ad hoc manner [4], Also, this approach cannot be generalised for any digit size. Hartley and Corbett [3] explored the digit- serial structures, where the digit size is restricted to be a divisor of the wordlength. Parhi [4] proposed a systematic approach, based on an unfolding transformation algorithm, to transform an arbitrary bit-serial architecture into a digit-serial architecture by unfolding with a factor equal to the digit size. The major drawback of these architectures is that they do not allow a high level of pipelining because of the feedback of the carry digit. This could reduce the efficiency of the digit-serial computation with respect to the throughput rate. In this Letter, a new cell architecture for high performance digit-serial computation is presented. By feeding the carry digit forward, the proposed architecture offers the possibility of pipelining to the bit level. This will increase the throughput rate of the digit-serial systems. The number of pipelining levels is only limited by the area constraint. The proposed architec- ture will give systems designers an extra parameter, namely the number of pipelining levels, which can be adjusted to find the best tradeoff between the throughput rate and the hard- ware cost. New cell architecture for digit-serial systems: The proposed digit serial cell architecture is based on an array multiplier as shown in Fig. 1. It uses the fact that the full adders at the boundaries of the array multiplier have free bit positions. In the conventional array multiplier, an adder is required to compute the most significant bits of the product from the two sets of bits that come out of the lower boundary of the array. In this Letter, these two sets of bits are termed the carry digit 938 ELECTRONICS LETTERS 27th May 1993 Vol.29 No. 11