Sensor Networks-Inspired Low-Power Robust PN Code Acquisition Sriram Narayanan, Girish V. Varatkar, Douglas L. Jones and Naresh R. Shanbhag Coordinated Science Laboratory/ECE Department University of Illinois at Urbana-Champaign 1308 W Main St., Urbana IL 61801 E-mail:[spnaraya, varatkar, dl-jones, shanbhag]@uiuc.edu Abstract-Algorithmic Noise Tolerance (ANT) techniques have reduced power consumption in many signal-processing applica- tions, but they typically require an error-free estimator block and do not fully exploit the statistical nature of timing errors. By approaching certain computations as estimation problems, we draw inspiration from sensor networks and develop a novel power conservation scheme in which the main computation result is estimated from multiple potentially erroneous sub-computations. The sub-computations are performed by "sensors" and a "fusion center" acts as a robust estimator. This scheme is shown to offer significant power savings in a PN code acquisition application. I. INTRODUCTION Increased transistor density and lagging battery technology have made power reduction an important concern in modern VLSI systems. At the same time, scaling in the nanometer regimes has introduced numerous source of nonidealities such as process variations and soft errors caused by particle hits. The ill-effects of some of these nonidealities may be overcome by overprovisioning power and designing with margins. But given the already severe power constraints, such techniques are often unacceptable. Therefore, we need novel approaches to striking optimal power/reliability trade-off. Dynamic voltage/frequency scaling techniques offered power savings by adjusting the supply voltage or clock frequency according to computational demand [1]. These methods exploit the fact that moderate supply voltage scaling can be performed without incurring excessive performance degradation in terms of increased gate delays. Modern VLSI systems demand more aggressive scaling and so need system- level approaches to tolerating errors. Error-tolerant approaches target more aggressive power sav- ings by scaling supply voltage in regimes where occasional er- rors do occur. Algorithmic Noise Tolerance (ANT) techniques [2] pair a voltage overscaled main DSP block with a lower- complexity estimator block. The outputs of these blocks are compared and if the main block is found to be erroneous, the output of the estimator block is used instead. Recently proposed Better Than Worst-Case design techniques [3] use a checker block to keep track of safe system-states and if the main block is found to be in error, the system is scaled back This research is supported by the Gigascale System Research Center (GSRC), one of five research centers funded under the Focus Center Re- searchxs Program (FCRP), a Semiconductor Research Corporation program, and Texas Instruments, Inc. to a previous safe-state. While these methods provide added gains over error-avoidance techniques by allowing sporadic hardware errors, they require explicit duplication of compu- tation (estimator or checker block). They also do not fully exploit the statistical nature of the problem because they only use one estimator. In a different context, sensor networks are capable of estimating physical phenomena based on distributed sensors. They distribute sensing among many low-power, unreliable nodes and apply estimation theory to form reliable estimates from these data. Perhaps, viewing computation as a special form of estimation by distributing it among several low-power nodes can offer analogous error-tolerance and power-efficiency to VLSI systems. II. STOCHASTIC SENSOR NETWORK-ON-CHIP Many DSP applications can be divided into sub-blocks. Examples of this include parallel architectures and polyphase decomposition of FIR filters. Often, the outputs of these sub- blocks may serve as low-fidelity estimates of the overall output. This approach generalizes traditional ANT systems by providing multiple parallel estimates of the final output. This novel view of computation enables us to borrow algorithms from estimation theory for use in the VLSI design context. In this work, we seek power savings by aggressively scaling supply voltage at the sub-blocks and allowing sporadic errors. Figure 1 illustrates the sensor-networks inspired circuit design approach. The sensors produce noisy estimates of the overall computation as denoted by the gray regions surrounding the black dots. The errors in the outputs of the sensors are due to the estimation error caused by lower-complexity sensors and hardware errors due to process variations, soft errors, and voltage scaling. The fusion center infers the final result based on these estimates. In the absence of large-magnitude timing errors, the mean of the estimates will be a good estimate of the final result (in the case of polyphase filters, exactly equal to the result). Since Voltage Overscaling (VOS) errors tend to be sporadic and are drawn from some unknown large-variance distribution [4] we instead apply methods from Robust Statistics [5] in the fusion center. III. HARDWARE NOISE MODEL The relationship between supply voltage and VOS errors was studied in [4]. Due to the LSB-first nature of most 978-1-4244-2110-7/08/$25.00 C2007 IEEE 1397