Citation: Rashid, M.; Sonbul, O.S.; Zia, M.Y.I.; Arif, M.; Sajid, A.; Alotaibi, S.S. Throughput/Area- Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2 233 ) on FPGA. Electronics 2023, 12, 3611. https://doi.org/10.3390/ electronics12173611 Academic Editor: Grzegorz H. Kasprowicz Received: 10 July 2023 Revised: 19 August 2023 Accepted: 24 August 2023 Published: 26 August 2023 Copyright: © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). electronics Article Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF (2 233 ) on FPGA Muhammad Rashid 1, * , Omar S. Sonbul 1 , Muhammad Yousuf Irfan Zia 2,3, * , Muhammad Arif 4 , Asher Sajid 5 and Saud S. Alotaibi 6 1 Computer Engineering Department, Umm Al Qura University, Makkah 21955, Saudi Arabia; ossonbul@uqu.edu.sa 2 Department of Electrical Engineering, Ziauddin University, Karachi 74600, Pakistan 3 Telecommunications Engineering School, University of Málaga, 29010 Málaga, Spain 4 Computer Science Department, Umm Al Qura University, Makkah 21955, Saudi Arabia; mahamid@uqu.edu.sa 5 Deanship of Scientific Research, Umm Al Qura University, Makkah 21955, Saudi Arabia; malikasher267@gmail.com 6 Department of Information Systems, Umm Al Qura University, Makkah 21955, Saudi Arabia; ssotaibi@uqu.edu.sa * Correspondence: mfelahi@uqu.edu.sa (M.R.); yousuf.irfan@zu.edu.pk or yirfanzia@uma.es (M.Y.I.Z.) Abstract: This paper presents a throughput/area-efficient hardware accelerator architecture for ellip- tic curve point multiplication (ECPM) computation over GF(2 233 ). The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba mod- ular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation. An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clock cycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59 μs, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations. Keywords: hardware design; elliptic curve cryptography; point multiplication; crypto processor; FPGA 1. Introduction The rapid increase in applications related to information technology has dramatically influenced the economy and culture in recent years [1]. This rapid increase has opened several security doors, leading to new critical threats for the community. Amongst several others, cryptography is one technique that offers secure information sharing on many elec- tronic devices [2,3]. Therefore, two types of cryptographic algorithms exist: (i) symmetric key and (ii) asymmetric key. Symmetric key cryptographic algorithms utilize a single key for encryption and decryption. They are prevalent because of their high speed and ease of use. However, they require the two parties to agree on a secret key beforehand, which can be challenging. On the other hand, asymmetric cryptographic algorithms utilize two different keys, i.e., a private key and a public key. The public key is widely known and used to encrypt the original message. Similarly, the encrypted message can only be converted Electronics 2023, 12, 3611. https://doi.org/10.3390/electronics12173611 https://www.mdpi.com/journal/electronics