390 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 6, JUNE 2004 Change in Transfer and Low-Frequency Noise Characteristics of n-Channel Polysilicon TFTs Due to Hot-Carrier Degradation A. Hatzopoulos, N. Archontas, N. A. Hastas, C. A. Dimitriadis, Member, IEEE, G. Kamarinos, N. Georgoulas, and A. Thanailakis Abstract—Results on the impact of hot-carrier effects on the transfer and low-frequency noise characteristics of n-channel poly- crystalline silicon thin-film transistors (polysilicon TFTs) are pre- sented. After stressing at the condition of maximum substrate cur- rent, the experimental data show that TFTs suffer from substantial on-current reduction. Through numerical simulation, it is shown that the stress-induced degradation increases the density of the band tail traps in a region extending 200 nm from the drain and the series resistance on the drain side. It is found that the origin of the noise is reverted from carrier number fluctuation for the un- stressed to the mobility fluctuation for the stressed device. Index Terms—Degradation, low-frequency noise, polysilicon, substrate current, thin-film transistor (TFT). I. INTRODUCTION P OLYCRYSTALLINE silicon thin-film transistors (polysil- icon TFTs) are of great interest for flat-panel displays with integrated drivers fabricated on inexpensive large glass substrates. For these applications, there is a particular demand for high stability and low-noise devices. However, it is widely reported that hot-carrier (HC) stressing results in a marked TFT degradation, arising from impact ionization in the high electric field region close to the drain junction [1]–[3]. Moreover, low-frequency noise (LFN) measurements can be used for analysis of HC-induced degradation in polysilicon TFTs [4]. As the substrate current has often been used for monitoring the HC-induced degradation [5], in this study we investigate the TFT degradation after stressing at gate and drain biases correlated with the maximum substrate current. II. EXPERIMENTAL The devices used in this study were fabricated on oxidized glass substrates by depositing amorphous silicon film (50 nm thick) by low-pressure chemical vapor deposition at 425 C and pressure of 1.1 torr. Then, the specimens were crystallized by furnace annealing in nitrogen ambient at 600 C for 24 h, followed by KrF excimer laser irradiation with energy density Manuscript received February 23, 2004. The review of this letter was arranged by Editor J. Sin. A. Hatzopoulos, N. A. Hastas, and C. A. Dimitriadis are with the Department of Physics, University of Thessaloniki, 54124 Thessaloniki, Greece. G. Kamarinos is with IMEP, ENSERG, 38016 Grenoble Cedex 1, France. N. Archontas, N. Georgoulas, and A. Thanailakis are with the Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi, Greece. Digital Object Identifier 10.1109/LED.2004.828555 340 mJ/cm in air ambient. Structural analysis has shown that small grains of diameter about 100 nm coexist with larger grains of mean diameter about 2.5 m and with low in-grain defect density [6]. A standard NMOS process was used to fabricate devices with gate length m and width m. As gate insulator, 120-nm-thick SiO was formed by electron cyclotron resonance-plasma enhanced chemical vapor deposi- tion at 100 C. Details for the device fabrication processes are presented elsewhere [6]. In order to measure the substrate hole current, TFTs with area m m having a -polysilicon side con- tact were used. The transfer characteristics were measured at room temperature before stress and at selected times after stress using a computer-controlled system including a Keithley 617 electrometer and Keithley 230 voltage sources. The threshold voltage of the investigated transistors was found to be about 2 V. LFN measurements were performed at room temper- ature using a SR760 fast Fourier transform spectrum analyzer preceded by low-noise current–voltage converter and voltage amplifier. The gate and drain biases was supplied by CdNi battery to reduce external noise effects. III. RESULTS AND DISCUSSION Fig. 1(a) shows the variation of with of a polysilicon TFT, with the drain voltage as a parameter. A peak located at is observed owing to the competition between the increasing carrier concentration and the decreasing total elec- tric field when increases. A notable change is observed in the magnitude of and the distribution of the versus bell-shaped curve, as illustrated in Fig. 1(b). Note that, due to stressing, damage occurs in the form of creation of new inter- face and/or bulk traps, thereby altering the overall distribution of these effects near the drain. This causes an increase in and a simultaneous shift in the -peak. Moreover, numerical sim- ulations have shown that traps in TFTs enhance the avalanche carrier generation rate due to increase of the electric field near the drain [7]. Polysilicon TFTs were subjected to electrical stress under the bias conditions of V and V, corresponding to the maximum of Fig. 1. Typical plots of characteristics, measured before and after stressing, are shown in Fig. 2 with stress time as a parameter. After stressing the on-state current is reduced, whereas the subthreshold slope and the threshold voltage remain unchanged with stress time. 0741-3106/04$20.00 © 2004 IEEE