Verilog-A Model for a Switched-Capacitor DC-DC Converter Nicolae Braic*, Cristian Raducan*, Marius Neag*, Vlad Ionescu** *Technical University of Cluj-Napoca, Basis of Electronics Department, 400027, Romania E-mail: nicolae.braic@bel.utcluj.ro ** Infineon Technologies Romania ** E-mail: vlad.ionescu@infineon.com Abstract—This paper presents the development and validation of a Verilog-A behavioral model for a switched capacitor DC-DC converter. For each converter component block, a behavioral model was created and validated, comparing simulation results with the correspondent transistor level implementation. The model was developed to allow the control of the switches ON resistance and dead time between operation phases. Using the behavioral model, the impact on the output voltage ripple amplitude of the switches RON, dead time, capacitors ESR and output track parasitic resistance was evaluated. Keywords: Verilog-A model; switched capacitor converter; output ripple; dead time; ESR; switch RON; 1. Introduction One of the most important steps in the development of an IC is pre-silicon verification. However, running transistor- level simulations on a complex analog or mixed-signal IC is often not possible due to time and resource limitations [1]. In turn, this often results in significant differences between pre-silicon simulations and post- silicon measurements, which require another design iteration. But, in order to identify the root cause of the differences one needs to perform more extensive simulations, which, again, may not be possible or practical to run. This paper presents an alternative to this multiple-design-iterations approach, based on combining simulations with functional modelling of key analog blocks. The proposed approach is illustrated by a real-life case: the debugging of a switched-capacitor (SC) DC-DC converter for which the measured output voltage ripple was significantly larger than the values predicted by (an incomplete set of) simulations. For an effective debug one needs to identify the root cause of measurement- versus-simulation discrepancies without running exhaustive (usually unpractically long) simulations. In general, the goal is to quickly assess the sensitivity of key system features to circuit parameters most likely to be represented inaccurately in simulations. Here we focus on the sensitivity of output voltage ripple to parasitic resistance of metal tracks, dead time between clock phases, the ESR (Equivalent Series Resistance) of external capacitors, the ON resistance of MOS switches and the coupling between “switching” and “quiet” signals lines. The idea is to develop a behavioral model for each of the converter blocks so that all circuit parameters mentioned above are represented, then run systematically simulations that combine schematic and model representation of each cell, in order to derive sensitivity to circuit parameters and/or replicate measurement results effectively. 2. Switched-capacitor DC-DC converter To develop the Verilog-A model is necessary first to analyze the converter structure and its principle of operation. The switched capacitor converter structure is presented in Fig.1. One notices three main OTA + _ CFLY RL VOUT VFB VREF VBAT S1 / Ф2 S2 / Ф1 S3 / Ф2 S4 / Ф1 S5 / Ф2 R1 R2 1 : N M1 M2 Power mirror Switch matrix CL OUTOTA RESR CP CM RTRACK Fig. 1 SC DC-DC converter block diagram