IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 7, Issue 4, Ver. II (Jul. - Aug. 2017), PP 48-55 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-0704024855 www.iosrjournals.org 48 | Page An Improvised Bottleneck Routing Algorithm for virtual Buffer based energy efficient NoC’s B.Nageshwar Rao 1 and N.S.Murti Sarma 2 1 (Research Scholar, department of ECE, Rayalaseema University, Kurnool, Andhra Pradesh, India ) 2 (Professor Sreenidhi Institute of Science and Technology, Yamnampet, Ghatakesar, Hyderabad, India) Abstract: Network on chip technology will be a major factor in future communication system which is based on intra core system, But when comes to power usage this practical NoC system consumes considerably huge power , then the Architecture of the crossbar routers will directly increases with respect to the no of intra core system . When comes to bulky systems, the average power consumption in crossbar switches relatively high. While detailing the components of the routers we found that buffers in the input terminals leads to major power consumption, when we try to remove buffers in NoC routers, the overall performance will reduce due to the bottleneck Increase. To make These Network on Chip crossbars efficiently without degradation in performance we propose a better systematic approach in the crossbar switches by incorporating virtual Memory system as a substitute of conventional register based memory, this will leads to energy efficiency with increase in overall performance. We are going to apply this architecture in NoC system which based on 5 Intra core system, our proposed system reduced nearly 30% of overall power usage. Keywords: Low Power, Network on Chip, Bufferless, Bottleneck Algori I. Introduction The Multiprocessors systems and the communication blocks in the integrated chips are constantly growing, so that the reliable communication protocol needed for the efficient communications between the integrated chips. In modern integrated chips design scenarios the design methodologies focusing on the communication centric approach rather than the computation centric. Traditional communication connections are replaced by the bus based communication topology due to its higher efficiency in bandwidth, scaling, and multi-processing communications. The Network on Chip architecture largely used by the multiprocessor system called as Multiprocessor System on Chip (MPSoc). Figure (1) Base Architecture of Network on Chip system. NoC systems majorly depends on the packet switching for enhancing its communication amount the intra chip cores. The designing process of NoC chip was more important due to its power and area profiles. NoC crossbar consumes nearly 30 % of total chip power for its interconnections between all intra chips. Memory circuits that’s input buffers acts major role in NoC power Profile. Nearly 72% of leakage power caused by these type of buffers only, These characteristics of buffers leads to significant loss in energy efficiency of NoC System. The power consumption chart of these buffers directionally proportional with the data flow rate. Network on Chip was a communication platform that was mostly uses by the modern communication processors. Network on Chip mostly depends on the application and the architecture oriented. The NoC consists