Overhead and Performance Comparison of SET Fault Tolerant Circuits Used in Flash-based FPGAs Farouk Smith Mechatronics, Nelson Mandela University, Port Elizabeth, South Africa Email: Farouk.smith@mandela.ac.za Abstract—The aim of alternative fault tolerant techniques used in flash-based FPGAs, such as Single Event Transient (SET) filters, is to provide a resource savings advantage when compared to Triple Modular Redundancy (TMR). The purpose of this paper is to quantify, in terms of particular circuit characteristics, what the savings will be. The results suggest that the most important circuit characteristic to determine the gate count increase is the ratio of the number of primary outputs to the original circuit gate count, when considering a combinational circuit. When considering a sequential circuit, the most important circuit characteristic is the ratio of the number of Register Logic (RL) vs. Combinational Logic (CL) in the datapath. The theoretical study found that the DMR and delay element Guard Gate (GG) SET filter technique used in sequential circuits, proved more costly than TMR in terms of resource increase, when the ratio of the number of RL vs. CL is greater than 10% and 28% respectively. Chip-level synthesis of circuits using these filter techniques with one family of flash-based FPGAs shows no gate count cost benefit compared to TMR when the ratio of the number of RL vs. CL is greater than 13% and 15% respectively. Index Terms—Double Modular Redundancy (DMR), Field Programmable Gate Array (FPGA), Single Event Transient (SET), Single Event Upset (SEU), Triple Modular Redundancy (TMR) I. INTRODUCTION The reconfigurable nature of Field Programmable Gate Arrays (FPGAs), together with their relatively low cost and ease of implementation, provided the space industry with an attractive solution for high level computer systems applications. Unfortunately, FPGAs are susceptible to Single Event Effects (SEEs) such as Single Event Transients (SETs) and Single Event Upsets (SEUs). SETs are caused by charged particles depositing charge on circuit elements through ionization. These deposited charges causes elevated local voltage levels in the circuit elements, which leads to incorrect logic values [1]. In a Combinational Logic (CL) element, the charge Manuscript received June 6, 2020; revised July 18, 2020; accepted July 25, 2020. Corresponding author: Farouk Smith (email: Farouk.smith@ mandela.ac.za). will leak away (over several hundreds of picoseconds) and the element, and consequently the system, will return to a consistent state. However, when synchronous logic is disturbed by a SET on a clock edge, the temporary incorrect logic value is latched into the register. This incorrect value can then propagate through the rest of the system compromising its functional integrity. SETs that are erroneously latched by a register are called SEUs. High energetic particle strikes through a memory element such as the configuration memory of an FPGA, causing a bit flip, are also called SEUs. The response of a particular family of FPGAs to SEUs, is a function of its configuration memory [2]. For example, SRAM FPGAs are a family of FPGAs which have configuration memory that consists of SRAM cells. It has been shown that the configuration memory of SRAM based FPGAs is sensitive to SEUs, which causes a bit flip, when struck by an energetically charged particle [2], [3]. This could cause a change in functionality. Flash-based FPGAs, on the other hand, have configuration memory that consists of flash-based memory cells, which have been shown to be resistant to SEUs [4], [5]. However, previous tests have shown that flash-based FPGAs are sensitive to soft errors, or SETs, in the combinational user logic, and to SEUs in the sequential logic elements [6]. The focus of this paper is on the SET mitigation schemes used in flash-based FPGAs. In order to use flash-based FPGAs in a radiation environment, the mitigation must be applied to the user logic, as well as the memory elements. A well-known and common mitigation scheme for correcting the SET and SEU errors in FPGAs is Triple Modular Redundancy (TMR) [7]. The main disadvantage of TMR is the excessive area overhead. The hardened design has at least three times more area and power consumption than the original circuit, excluding TMR overhead. When the TMR hardened designs are implemented with a hardware description language or via the manufacturer’s software tools, it instantiates redundant triplicate circuits in the user design as well as voting circuits [8]. This method of implementing TMR results in four [9] to seven times [10] resource increase, which limits its usage to reliability-critical applications. International Journal of Electrical and Electronic Engineering & Telecommunications Vol. 10, No. 2, March 2021 ©2021 Int. J. Elec. & Elecn. Eng. & Telcomm. 76 doi: 10.18178/ijeetc.10.2.76-82