2168-2356 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/MDAT.2019.2908547, IEEE Design and Test Introducing Hardware based Intelligence and Reconfigurability on Industrial IoT Edge Nodes Apostolos P. Fournaris, Christos Alexakos, Christos Anagnostopoulos, Christos Koulamas, Athanasios Kalogeras Industrial Systems Institute ATHENA Research Center Patras, Greece {fournaris, alexakos, anagnostopoulos, koulamas, kalogeras}@isi.gr Abstract — Industrial automation and control environments has indicative examples of complex distributed systems where the IoT deployment pattern of edge measurements and cloud-based analytics does not always fit all requirements. Intelligent embedded devices executing critical functionality and communicating, in real-time or not, through well-structured network architectures are a commodity in manufacturing for decades. Nevertheless, the evolution and penetration of embedded and wireless communication technologies, marked as Industrial IoT (IIoT), calls for specific architectural adaptations to optimally exploit this technology landscape. In this paper we revisit an Industry 4.0 plant’s overall manufacturing chain and propose a system architecture supporting a mechanism that can efficiently migrate IIoT computation functionality and intelligence to the system’s edge nodes. Furthermore, in this paper we focus on embedded edge device architectures and propose the use of FPGA technology, supported in some embedded System on Chips (SoC), for transferring power hungry and computationally intensive smart operations. To achieve that we propose an edge node architecture and implementation for an abnormal device behavior (feature extraction, outlier detection) IIoT use case that realizes the proposed hardware/software codesign edge node approach and by collecting experimental results achieves benefits in terms of energy consumption and high responsiveness (speed) compared to traditional solutions. Keywords— IIoT; reconfigurable logic, VLSI design; edge IoT; fog IoT; adaptive manufacturing; systems integration; I. INTRODUCTION The need for advanced intelligence in the industrial environment may lead to moving intelligence from the cloud down to the local network level or directly into embedded devices. Thus, fog or edge computing emerges as a serious research challenge on edge nodes. This highlights the need for nodes that are capable of handling complex functions beyond simple sensing and actuation loops. Functionality for local and embedded processing of collected data to extract possible industrial decisions without the need for cloud communication is becoming a reality in current and future edge based IIoT deployments. However, this high edge node intelligence may have a considerable footprint on a device’s hardware resources, thus draining a node from battery, memory or processing power. Operations related to statistical manipulation of collected sensor data on the time domain (like Pearson’s Convolution, Kurtosis) as well as industrial process anomalies and embedded machine learning algorithms may introduce a very high toll on an edge node expected behavior (long life cycle, fast responsiveness etc.). Also, additional edge node features, like security strengthening, also introduce additional performance and hardware resource overhead that cannot always be handled by the IIoT edge device without compromises in other device non- functional requirements. In this paper, we present a system architecture that can handle the overall manufacturing chain of an Industry 4.0 plant and divide it into different layers, focusing on the level of intelligence that each layer can handle. On the above system, we propose a mechanism that can efficiently migrate IIoT computational functionality and Edge intelligence to the system end node devices. Since such devices do not always have the resources to support complex operations, we propose the executions of these operations through hardware means inside the node SoC. To bypass the lack of flexibility that ASICs have, we propose the use of FPGA technology on the end node device. Recent advancements in FPGA technology enable us to use SoC core designs that merge powerful ARM embedded processors with FPGA fabric. As an example of our proposed approach, we introduce a prototype concept of an edge node for our system that has hardware support for a statistical feature extraction mechanism and for detecting outlier behavior through novelty vector extraction using the extracted features and a training set of known good values. The nearest neighbor machine learning algorithm is used for the novelty extraction. Using this concept, we can support condition monitoring operations for industrial assets on the edge level. The above approach was prototyped on an actual embedded system setting (Smartfusion2 SoC board combined with the CC2538 based Openmote board for wireless communication) and the above two procedures (feature and novelty extraction) were realized in purely software and the proposed hardware/software codesigned way (using the Smartfusion2 SoC FPGA fabric). The experimental results confirmed that the proposed approach had considerable savings This work is supported by the project “Ι3 - Innovative Application of Industrial Internet of Things (IIoT) in Smart Environments” (MIS 5002434) implemented under the “Action for the Strategic Development on the Research and Technological Sector”, funded by the Operational Programme "Competitiveness, Entrepreneurship and Innovation" (NSRF 2014-2020) and co-financed by Greece and the European Union (European Regional Development Fund).